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Concept
Blackfin
Summary
The Blackfin is a family of 16-/32-bit microprocessors developed, manufactured and marketed by Analog Devices. The processors have built-in, fixed-point digital signal processor (DSP) functionality supplied by 16-bit multiply–accumulates (MACs), accompanied on-chip by a microcontroller. It was designed for a unified low-power processor architecture that can run operating systems while simultaneously handling complex numeric tasks such as real-time H.264 video encoding.
Blackfin processors use a 32-bit RISC microcontroller programming model on a SIMD architecture, which was co-developed by Intel and Analog Devices, as MSA (Micro Signal Architecture).
The architecture was announced in December 2000, and first demonstrated at the Embedded Systems Conference in June, 2001.
It incorporates aspects of ADI's older SHARC architecture and Intel's XScale architecture into a single core, combining digital signal processing (DSP) and microcontroller functionality. There are many differences in the core architecture between Blackfin/MSA and XScale/ARM or SHARC, but the combination was designed to improve performance, programmability and power consumption over traditional DSP or RISC architecture designs.
The Blackfin architecture encompasses various CPU models, each targeting particular applications. The BF-7xx series, introduced in 2014, comprise the Blackfin+ architecture, which expands on the Blackfin architecture with some new processor features and instructions.
What is regarded as the Blackfin "core" is contextually dependent. For some applications, the DSP features are central. Blackfin has two 16-bit hardware MACs, two 40-bit ALUs and accumulators, a 40-bit barrel shifter, and four 8-bit video ALUs; Blackfin+ processors add a 32-bit MAC and 72-bit accumulator. This allows the processor to execute up to three instructions per clock cycle, depending on the level of optimization performed by the compiler or programmer. Two nested zero-overhead loops and four circular buffer DAGs (data address generators) are designed to assist in writing efficient code requiring fewer instructions.
Official source
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