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Concept
Delay slot
Summary
In computer architecture, a delay slot is an instruction slot being executed without the effects of a preceding instruction. The most common form is a single arbitrary instruction located immediately after a branch instruction on a RISC or DSP architecture; this instruction will execute even if the preceding branch is taken. Thus, by design, the instructions appear to execute in an illogical or incorrect order. It is typical for assemblers to automatically reorder instructions by default, hiding the awkwardness from assembly developers and compilers.
When a branch instruction is involved, the location of the following delay slot instruction in the pipeline may be called a branch delay slot. Branch delay slots are found mainly in DSP architectures and older RISC architectures. MIPS, PA-RISC, ETRAX CRIS, SuperH, and SPARC are RISC architectures that each have a single branch delay slot; PowerPC, ARM, Alpha, and RISC-V do not have any. DSP architectures that each have a single branch delay slot include the VS DSP, μPD77230 and TMS320C3x. The SHARC DSP and MIPS-X use a double branch delay slot; such a processor will execute a pair of instructions following a branch instruction before the branch takes effect. The TMS320C4x uses a triple branch delay slot.
The following example shows delayed branches in assembly language for the SHARC DSP including a pair after the RTS instruction. Registers R0 through R9 are cleared to zero in order by number (the register cleared after R6 is R7, not R9). No instruction executes more than once.
R0 = 0;
CALL fn (DB); /* call a function, below at label "fn" /
R1 = 0; / first delay slot /
R2 = 0; / second delay slot /
/**** discontinuity here (the CALL takes effect) /
R6 = 0; / the CALL/RTS comes back here, not at "R1 = 0" /
JUMP end (DB);
R7 = 0; / first delay slot /
R8 = 0; / second delay slot /
/ discontinuity here (the JUMP takes effect) /
/ next 4 instructions are called from above, as function "fn" /
fn: R3 = 0;
RTS (DB); / return to caller, past the caller's delay slots /
R4 = 0; / first delay slot /
R5 = 0; / second delay slot /
/ discontinuity here (the RTS takes effect) *****/
end: R9 = 0;
The goal of a pipelined architecture is to complete an instruction every clock cycle.
Official source
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