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Progress in single-photon avalanche diode image sensors in standard CMOS: From two-dimensional monolithic to three-dimensional-stacked technology

Edoardo Charbon, Myung Jae Lee

Single-photon detection and photon counting are useful tools in many fields, from light detection and ranging (LiDAR) to biomedical imaging and from time-resolved Raman spectroscopy to quantum applications. In this context, recently, single-photon avalanch ...

IOP PUBLISHING LTD2018

Through-Glass Vias for Glass Interposers and MEMS Packaging Applications Fabricated Using Magnetic Assembly of Microscale Metal Wires

Mikhail Asiatici, Göran Stemme

A through-glass via (TGV) provides a vertical electrical connection through a glass substrate. TGVs are used in advanced packaging solutions, such as glass interposers and wafer-level packaging of microelectromechanical systems (MEMS). However, TGVs are ch ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

An FPGA-Based Test System for RRAM Technology Characterization

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Maxime Victor Thammasack, Armando Biscontini

Resistive random access memory (RRAM) technologies have recently gained large attention from the academic and industrial research communities. Significant efforts have been made to enhance the performance of the memory stacks from both communities through ...

2018

Experimental characterisation of the thermohydraulic performance of a micro-pin fin evaporator: Heat transfer, flow visualization and modelling

Chiara Falsetti

The global tendency towards miniaturization driven by the microelectronics industry is pushing system density and packaging towards unprecedented values of thermal design power, with a dramatic reduction of the surface area of the devices. Vertical integra ...

EPFL2018

Through Silicon Vias With Invar Metal Conductor for High-Temperature Applications

Mikhail Asiatici, Göran Stemme

Through silicon vias (TSVs) are key enablers of 3-D integration technologies which, by vertically stacking and interconnecting multiple chips, achieve higher performances, lower power, and a smaller footprint. Copper is the most commonly used conductor to ...

Institute of Electrical and Electronics Engineers2017

Copper TSV-Based Process Development for Die-Level Homogeneous and Heterogeneous 3D Integration Platform

Seniz Esra Küçük

Research and development efforts on chip and wafer-scale 3D integration for system miniaturization have been continuing for more than a decade. However, there are still only a handful of 3D integrated products available in the market due to the high cost a ...

EPFL2017

Magnetization loss for stacks of ReBCO tapes

Pierluigi Bruzzone, Davide Uglietti

The AC loss measurements of the high temperature superconductor (HTS) cable prototype in the EDIPO test facility motivated detailed investigations of the loss contributions from the tape, strand and cable stages of the HTS fusion conductor design proposed ...

2017

A Chip-Level Post-CMOS Via-Last Cu TSV Process for Multi-Layer Homogeneous 3D Integration

Seniz Esra Küçük, Yusuf Leblebici, Woo Yeong Cho

In this paper, a die-level CMOS post-processing scheme for 3D integration using the via-last approach is presented for multi-layer stacking. The process includes TSV fabrication, chip-to-chip bonding, and finally the TSV filling with Cu electroplating. The ...

Ieee2016

Storage method and apparatus for random access memory using codeword storage

Harm Cronie

A memory circuit, such as an embedded DRAM array, stores information as groups of bits or data using information coding in storage and retrieval data, instead of each bit being stored separately. Write data words can be mapped to storage format words that ...

2016

Copper TSV-Based Die-Level Via-Last 3D Integration Process with Parylene-C Adhesive Bonding Technique

Yusuf Leblebici, Seniz Esra Küçük

This paper presents a die-level post-CMOS processing protocol for multi-layer homogeneous 3D integration with adhesive bonding technique using parylene-C as an intermediate bonding layer and sidewall passivation material. This protocol was used to fabricat ...

2016

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