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Simulation of Double-Gate Silicon Tunnel FETs with a High-k Gate Dielectric

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Simulation of Double-Gate Silicon Tunnel FETs with a High-k Gate Dielectric

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Lateral Strain Profile as Key Technology Booster for All-Silicon Tunnel FETs

Bias stress effect in low-voltage organic thin-film transistors

Analysis of degradation mechanisms in lattice-matched InAlN/GaN high-electron-mobility transistors

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

Current collapse reduction in InAlN/GaN MOS HEMTs by in situ surface pre-treatment and atomic layer deposition of ZrO2 high-k gate dielectrics

102-GHz AlInN/GaN HEMTs on Silicon With 2.5-W/mm Output Power at 10 GHz

Double-Gate Pentacene TFTs with Improved Control in Subthreshold Region

Subthreshold SCL for Ultra-Low-Power SRAM and Low-Activity-Rate Digital Systems

Investigation of bias-dependent series resistances and barrier height in Double Gate Schottky MOSFETs

Investigation of bias-dependent series resistances and barrier height in Double Gate Schottky MOSFETs

Leakage Current Reduction Using Subthreshold Source-Coupled Logic

Investigation of bias-dependent series resistances and barrier height in Double Gate Schottky MOSFETs

Bias stress effect in low-voltage organic thin-film transistors

Investigation of bias-dependent series resistances and barrier height in Double Gate Schottky MOSFETs

Analysis of degradation mechanisms in lattice-matched InAlN/GaN high-electron-mobility transistors

Subthreshold SCL for Ultra-Low-Power SRAM and Low-Activity-Rate Digital Systems

102-GHz AlInN/GaN HEMTs on Silicon With 2.5-W/mm Output Power at 10 GHz

Lateral Strain Profile as Key Technology Booster for All-Silicon Tunnel FETs

Current collapse reduction in InAlN/GaN MOS HEMTs by in situ surface pre-treatment and atomic layer deposition of ZrO2 high-k gate dielectrics

Double-Gate Pentacene TFTs with Improved Control in Subthreshold Region