Design and Implementation of CMOS Image Sensors for Biomedical Applications

Since the first introduction of digital cameras, the camera market has been taking tremendous interest from many fields. This trend has even accelerated when the cost, size, and power consumption of such devices were reduced with the introduction of camera on a chip concept. This concept is achieved by integrating photoactive and electronics parts of digital cameras on a single chip with Complementary Metal Oxide Semiconductor (CMOS) technology but resulted in reduced photon collection efficiency and increased noise. Since then, scientists and researchers have been putting a huge effort to improve the quality of CMOS image sensors with advancements in lithography and fabrication process, by finding alternative ways of increasing the fill factor, designing lower noise circuits, and putting additional on chip features. Despite these efforts and cost, integration, and power consumption advantages of CMOS image sensors, they have still not been preferred in many application fields such as biomedical imaging, where high quality imaging is targeted. Recently, with the process related technological advancements, the cost of CMOS image sensors have increased and this has made the CMOS image sensors loose their cost advantage and attractiveness for low cost applications. In this thesis, I summarize my research effort in integrating the low-cost CMOS image sensors in biomedical applications and improving their performance with novel circuits fabricated with standard CMOS process, while maintaining their cost advantage. Towards this aim, I propose possible ways of implementing pixel array sensors and noise reduction and read-out related circuits with standard CMOS technology in order to make these low-cost sensors applicable for biomedical applications. For this purpose, this research started by fabricating a characterization chip that uses standard CMOS process compatible photodiodes and pixels. Using this chip, I obtained characterization data for an n-well 0.18μm standard CMOS technology and made it available for designers using similar technologies. Later, I developed a small camera prototype by using the characterization data of the first chip. This small camera chip includes efficient pixel circuits with column parallel fully differential noise reduction circuits, and horizontal and vertical access circuits. After obtaining good quality images using this camera prototype, I designed a larger array camera chip, which offers Video Graphics Array (VGA) resolution, using the same technology. This third camera chip uses pixel sharing technique, which results in 1.75 transistors per pixel. Moreover, this design provides the flexibility of changing the pixel array resolution with respect to the pixel size, aiming to optimize the performance according to the application. In order to result in highest possible fill factor, all of these fabricated chips use Active Pixel Sensor (APS) technique. Within the scope of this thesis, I also propose novel Digital Pixel