Publications related to Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

Exploring brain-inspired multi-core heterogeneous hardware templates for low-power biomedical embedded systems

The miniaturization of integrated circuits (ICs) and their higher performance and energy efficiency, combined with new machine learning algorithms and applications, have paved the way to intelligent, interconnected edge devices. In the medical domain, they ...

EPFL2023

Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs

Mathias Josef Payer, Mirjana Stojilovic, Shashwat Shrivastava, Ognjen Glamocanin, Jinwei Yao, Nour Ardo

Side-channel disassembly attacks recover CPU instructions from power or electromagnetic side-channel traces measured during code execution. These attacks typically rely on physical access, proximity to the victim device, and high sampling rate measuring in ...

2023

Computational Imaging SPAD Cameras

Andrei Ardelean

Vision systems built around conventional image sensors have to read, encode and transmit large quantities of pixel information, a majority of which is redundant. As a result, new computational imaging sensor architectures were developed to preprocess the r ...

EPFL2023

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

Thermal and Voltage-Aware Performance Management of 3D MPSoCs with Flow Cell Arrays and Integrated SC Converters

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Halima Najibi

Flow cell arrays (FCAs) concurrently provide efficient on-chip liquid cooling and electrochemical power generation. This technology is especially promising for three-dimensional multi-processor systems-on-chip (3D MPSoCs) realized in deeply scaled technolo ...

2022

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Rafael Medina Morillas, Yasir Mahmood Qureshi, Joshua Alexander Harrison Klein

In order to develop sustainable and more powerful information technology (IT) infrastructures, the challenges posed by the "memory wall" are critical for the design of high-performance and high-efficiency many-core computing systems. In this context, recen ...

IEEE2022

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud, David Dervishi

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

2022

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Paolo Ienne, Mikhail Asiatici, Damian Maiorano

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

SPRINGER2021

Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities

Mikhail Asiatici

Even if Dennard scaling came to an end fifteen years ago, Moore' s law kept fueling an exponential growth in compute performance through increased parallelization. However, the performance of memory and, in particular, Dynamic Random Access Memory (DRAM), ...

EPFL2021

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Mohamed Mostafa Sabry Aly, Halima Najibi

Deeply-scaled three-dimensional (3D) Multi-Processor Systems-on-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However, as process nodes shrink, temperature-dependent leakage dramatically increases, ...

2020