Publications associées à Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache

Hierarchical Thermal Management Policy for High-Performance 3D Systems with Liquid Cooling

Giovanni De Micheli, David Atienza Alonso, Mohamed Mostafa Sabry Aly, Francesco Zanini

3-Dimensional integrated circuits and systems are expected to be present in electronic products in the short term. We consider specifically 3-D multi-processor systems-onchip (MPSoCs), realized by stacking silicon CMOS chips and interconnecting them by mea ...

2011

Simulation of High-Performance Memory Allocators

David Atienza Alonso, José Luis Risco Martin

This study presents a single-core and a multi-core processor architecture for health monitoring systems where slow biosignal events and highly parallel computations exist. The single-core architecture is composed of a processing core (PC), an instruction m ...

Elsevier2011

A mixed-signal platform dedicated to power system dynamic computation

Maher Kayal, Cédric Meinen, Laurent Fabre, Ira Nagel

has already been proven that analog emulation overcomes the speed limits of numerical simulators by means of a simple fixed-topology prototype. In order to enhance the modularity and the size of the emulated power system a dedicated platform based on a fie ...

IEEE2011

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Networks-on-Chip (NoC), being a system-level interconnect, can play a major role in achieving low-power SoC designs. In many designs, the cores are grouped in to Voltage Islands (VIs). To reduce the leakage power consumption, an island containing cores tha ...

Springer New York2011

CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips

Giovanni De Micheli, Babak Falsafi, Ciprian Seiculescu, Stavros Volos, Naser Khosro Pour

Manycore chips are emerging as the architecture of choice to provide power-scalability and improve performance while riding the Moore’s law. On-chip interconnects are increasingly playing a pivotal role in power- and performance- scalability of such microa ...

2011

3D Integration Technology for Lab-on-a-Chip Applications

Carlotta Guiducci, Yusuf Leblebici, Yüksel Temiz, Samuel Kilchenmann

A review is presented of advances and challenges in fully integrated systems for personalised medicine applications. One key issue for the commercialisation of such systems is the disposability of the assay-substrate at a low cost. This work adds a new dim ...

Institution of Engineering and Technology2011

Reliability in the Dark Silicon Era

Babak Falsafi

Information technology is now an indispensable pillar of a modern-day society, thanks to the proliferation of digital platforms in the past several decades. The demand on robust and economical data processing and storage, however, is growing faster than te ...

IEEE Computer Soc Press, Customer Service Center, Po Box 3014, 10662 Los Vaqueros Circle, Los Alamitos, CA 907202011

Performance and Energy Trade-offs Analysis of L2 on-Chip Cache Architectures for Embedded MPSoCs

Martino Ruggiero, Mohamed Mostafa Sabry Aly, Pablo Garcia del Valle

On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multi-processor systems. Following the trend set by high-performance processors, high-end embedded cores are moving from single-level on chip ...

2010

TurboTag: Lookup Filtering to Reduce Coherence Directory Power

Babak Falsafi, Michael Ferdman, Pejman Lotfi Kamran, Daniel Crisan

On-chip coherence directories of today’s multi-core systems are not energy efficient. Coherence directories dissipate a significant fraction of their power on unnecessary lookups when running commercial server and scientific workloads. These workloads have ...

ACM2010

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Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache

Hierarchical Thermal Management Policy for High-Performance 3D Systems with Liquid Cooling

Simulation of High-Performance Memory Allocators

A mixed-signal platform dedicated to power system dynamic computation

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips

3D Integration Technology for Lab-on-a-Chip Applications

Reliability in the Dark Silicon Era

Architectural Support for Coherent Architecturally Visible Storage in Instruction Set Extensions

Performance and Energy Trade-offs Analysis of L2 on-Chip Cache Architectures for Embedded MPSoCs

TurboTag: Lookup Filtering to Reduce Coherence Directory Power

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Chattez avec Graph Search

A mixed-signal platform dedicated to power system dynamic computation

Simulation of High-Performance Memory Allocators

Hierarchical Thermal Management Policy for High-Performance 3D Systems with Liquid Cooling

TurboTag: Lookup Filtering to Reduce Coherence Directory Power

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips

Architectural Support for Coherent Architecturally Visible Storage in Instruction Set Extensions

Performance and Energy Trade-offs Analysis of L2 on-Chip Cache Architectures for Embedded MPSoCs

Reliability in the Dark Silicon Era

3D Integration Technology for Lab-on-a-Chip Applications