Stretch: Balancing QoS and Throughput for Colocated Server Workloads on SMT Cores

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STEPS 4.0: Fast and memory-efficient molecular simulations of neurons at the nanoscale

Felix Schürmann, James Gonzalo King, Pramod Shivaji Kumbhar, Omar Awile, Christos Kotsalos, Tristan Mathieu Carel, Iain Hepburn, Samuel Marie A Melchior, Weiliang Chen, Baudouin Paul Michel Maria Joseph Del Marmol

Recent advances in computational neuroscience have demonstrated the usefulness and importance of stochastic, spatial reaction-diffusion simulations. However, ever increasing model complexity renders traditional serial solvers, as well as naive parallel imp ...

FRONTIERS MEDIA SA2022

Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Rafael Medina Morillas, Yasir Mahmood Qureshi, Joshua Alexander Harrison Klein

In order to develop sustainable and more powerful information technology (IT) infrastructures, the challenges posed by the "memory wall" are critical for the design of high-performance and high-efficiency many-core computing systems. In this context, recen ...

IEEE2022

A lightweight learning-based decoding algorithm for intraneural vagus nerve activity classification in pigs

Silvestro Micera, Leonardo Pollina, Ivo Strauss

Objective. Bioelectronic medicine is an emerging field that aims at developing closed-loop neuromodulation protocols for the autonomic nervous system (ANS) to treat a wide range of disorders. When designing a closed-loop protocol for real time modulation o ...

IOP Publishing Ltd2022

Sampling-Based AQP in Modern Analytical Engines

Anastasia Ailamaki, Viktor Sanca

As the data volume grows, reducing the query execution times remains an elusive goal. While approximate query processing (AQP) techniques present a principled method to trade off accuracy for faster queries in analytics, the sample creation is often consid ...

ACM2022

DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks

Mirjana Stojilovic, Dina Gamaleldin Ahmed Shawky Mahmoud, David Dervishi

Field-programmable gate arrays (FPGAs) combine hardware reconfigurability with a high degree of parallelism. Consequently, FPGAs offer performance gains and power savings for many applications. A recent trend has been to leverage the hardware versatility o ...

2022

Boosting Efficiency of External Pipelines by Blurring Application Boundaries

Anastasia Ailamaki, Anna Patricia Herlihy, Periklis Chrysogelos

Modern application development addresses increasingly specialized problems using domain-specific utilities, such as Optical Code Recognition and standalone statistical tools. The diversity of tooling, combined with the ever-growing volume of data, requires ...

2022

Architecture Exploration and Optimization of Heterogeneous Many-Core Compute and Memory Architectures with Architectural Extensions

Yasir Mahmood Qureshi

The expeditious proliferation of Internet connectivity and the growing adoption of digital products have transformed various spheres of our everyday lives. This increased digitization of society has led to the emergence of new applications, which are deplo ...

EPFL2021

Micro-architectural Analysis of Database Workloads

Utku Sirin

Database workloads have significantly evolved in the past twenty years. Traditional database systems that are mainly used to serve Online Transactional Processing (OLTP) workloads evolved into specialized database systems that are optimized for particular ...

EPFL2021

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

Paolo Ienne, Mikhail Asiatici, Damian Maiorano

String sorting is a fundamental kernel of string matching and database index construction; yet, it has not been studied as extensively as fixed-length keys sorting. Because processing variable-length keys in hardware is challenging, it is no surprise that ...

SPRINGER2021

High-Level Synthesis of Dynamically Scheduled Circuits

Lana Josipovic

High-Level Synthesis (HLS) tools generate hardware designs from high-level programming languages. These tools almost universally build datapaths that are controlled using a centralized controller which relies on a static, compile-time schedule to determine ...

EPFL2021

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Boosting Efficiency of External Pipelines by Blurring Application Boundaries

Anastasia Ailamaki, Anna Patricia Herlihy, Periklis Chrysogelos

2022

Architecture Exploration and Optimization of Heterogeneous Many-Core Compute and Memory Architectures with Architectural Extensions

Yasir Mahmood Qureshi

EPFL2021