An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits

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Highly Parallel RTL Simulation

Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL. As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and ...

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Resource Sharing in Dataflow Circuits

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To achieve resource-efficient hardware designs, high-level synthesis (HLS) tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed in conjunction with operation scheduling to ensure th ...

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Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

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The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

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From C/C plus plus Code to High-Performance Dataflow Circuits

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High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

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SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

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Writing and optimizing application software for heterogeneous platforms including GPU units is a very difficult task that requires designer efforts and resources to consider several key elements to obtain good performance. Dataflow programming has shown to ...

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Inter-actions parallel execution on GPU from high-level dataflow synthesis

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Recent GPU architectures make available numbers of parallel processing units that exceed by orders of magnitude the ones offered by CPU architectures. Whereas programs written using dataflow programming languages are well suited for programming heterogeneo ...

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DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

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A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

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Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

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Developing and fine-tuning software programs for heterogeneous hardware such as CPU/GPU processing platforms comprise a highly complex endeavor that demands considerable time and effort of software engineers and requires evaluating various fundamental comp ...

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Uncooperative Rendezvous in Space: Design of an Electronic Architecture for High Performance Avionic with Multi Sensor Input and Intensive Data Rate

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Active Debris Removal missions consist of sending a satellite in space and removing one or more debris from their current orbit. A key challenge is to obtain information about the uncooperative target. By gathering the velocity, position, and rotation of t ...

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Resource Sharing in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Axel Marmet

To achieve resource-efficient hardware designs, HLS tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed together with operation scheduling to ensure the best possible unit usage at ...

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Uncooperative Rendezvous in Space: Design of an Electronic Architecture for High Performance Avionic with Multi Sensor Input and Intensive Data Rate

Michaël Yannick Juillard

EPFL2022

Resource Sharing in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Axel Marmet

IEEE2022