Generating a CLK Generator (PLL) IP in Vivado

In course

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Description

This lecture covers the process of generating a Clock Generator (PLL) IP in Vivado using the Clocking Wizard tool. The instructor demonstrates how to create, simulate, synthesize, implement, and debug the clocking circuit customized to the user's requirements.

Instructor

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Official source

https://mediaspace.epfl.ch/media/0_3tpgtq8s

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Ontological neighbourhood

Computer engineering

Hardware engineering: Application-specific integrated circuit

Computer graphics: Virtual reality

Theoretical computer science

Programming language theory: High-level programming languages

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