Cache Coherence

This lecture on cache coherence covers the problem of sharing data in multiprocessor caches, the basic solution of scaling to many CPUs, and the concept of directories. It explains the incoherence problem with examples and introduces the Single Writer, Multiple Reader (SWMR) Invariant. The lecture delves into mechanisms for basic coherence, including the Valid and Invalid Protocol, and provides examples of its implementation. It also discusses the MSI Protocol, the challenges of interconnect scaling, and the concept of Distributed Duplicate Tag Directories. The lecture concludes with a summary of cache coherence protocols and the importance of maintaining a unified view of memory locations.