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This paper reports a new post-CMOS processing platform for die-level through-silicon-via (TSV) fabrication, based on wafer reconstitution from embedded dies, parylene deposition, stencil lithography, and bottom-up electroplating. The goal of this work is to develop a heterogeneous 3D-integration technique for the applications requiring CMOS-MEMS integration with vertical interconnections.
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Edoardo Charbon, Sandro Carrara, Simone Frasca, Rebecca Camilla Leghziel