A 4.1 pJ/b 25.6 Gb/s 4-PAM Reduced-State Sliding-Block Viterbi Detector in 14 nm CMOS

The implementation of a digital four-level pulse-amplitude-modulation reduced-state sliding-block Viterbi detector (VD) with two substates and two embedded per-survivor decision-feedback taps operating at one-eighth of the modulation rate is described. Implemented in an experimental chip fabricated in 14nm CMOS, the VD is designed to recover data at 25.6 Gb/s over an emulated time-dispersive channel. The power consumption of the VD together with the test circuitry is 105mW at a supply of 0.7V, achieving an overall energy efficiency of 4.1 pJ/b. At a supply of 0.8V, a data rate of 30.4 Gb/s is achieved with an energy efficiency of 5.3 pJ/b. The VD occupies an area of 0.507 +/- 0.717mm(2). Experimental results showing system performance are obtained using a (2(15)-1)-bit pseudo-random binary sequence. The impact on the bit error rate of the synchronization length for block initialization is also measured.