Nanopillars Enabling III-V Integration on Si (100) and (111)

The majority of current semiconductor technologies are built on Si (100), such as the CMOS technology, or conventional solar cell devices. III-V semiconductors offer great perspectives given their high carrier mobility and direct band gap. However their integration on Si remains a challenge: defects due to the lattice mismatch and cost, among others. We explore the growth of nanostructures using molecular beam epitaxy as a potential solution. Nanostructures possess a very low footprint, limiting defects at the interface and throughout the active material. If grown using the VLS mechanism, the catalyst droplet configuration permit to engineer the crystal phase in wurtzite or zinc-blende, opening perspectives for III-V phase-engineering. In this work we studied the use of Si nanopillars as a patterning method in order to grow vertical nanostructures on Si (100) that we coined nanospades. Nanospades exhibit a bi-crystal structure and a high crystalline purity, making them great candidates for optoelectronics on Si (100). Therefore we grew InGaAs heterostructures on Si (100) using vertical nanospades as templates and demonstrated optically-active structures that emit in the infrared. We unveiled an emission spatial splitting in the emission spectra throughout the nanospade. We correlated this feature with the unique crystalline structure of the nanospade and show the potential for manufacturing dual wavelength light-emitting diodes. We also explored the use of Si nanopillars on Si (111) for growing large-area GaAs nanowire arrays. We first identified the key parameters and fundamental aspects of nanowires growth on Si pillars by electron-beam lithography where we reached vertical yields of 55%. We showed that the droplet configuration, i.e contact angle and triple phase line, are central for a successful growth, and that the pillar geometry permits to engineer the droplet contact angle. We compared our experiments with simulations performed in Surface Evolver and observed a strong correlation. We then manufactured SiO2/Si pillars using phase-shift lithography and grew large-area GaAs nanowire arrays. We reached a maximum local vertical yield of 67% and a global chip-scale yield of 40%. We also unveiled the potential for phase engineering using the pillar geometry.