FMA instruction set

The FMA instruction set is an extension to the 128 and 256-bit Streaming SIMD Extensions instructions in the x86 microprocessor instruction set to perform fused multiply–add (FMA) operations. There are two variants: FMA4 is supported in AMD processors starting with the Bulldozer architecture. FMA4 was performed in hardware before FMA3 was. Support for FMA4 has been removed since Zen 1. FMA3 is supported in AMD processors starting with the Piledriver architecture and Intel starting with Haswell processors and Broadwell processors since 2014. FMA3 and FMA4 instructions have almost identical functionality, but are not compatible. Both contain fused multiply–add (FMA) instructions for floating-point scalar and SIMD operations, but FMA3 instructions have three operands, while FMA4 ones have four. The FMA operation has the form d = round(a · b + c), where the round function performs a rounding to allow the result to fit within the destination register if there are too many significant bits to fit within the destination. The four-operand form (FMA4) allows a, b, c and d to be four different registers, while the three-operand form (FMA3) requires that d be the same register as a, b or c. The three-operand form makes the code shorter and the hardware implementation slightly simpler, while the four-operand form provides more programming flexibility. See XOP instruction set for more discussion of compatibility issues between Intel and AMD. AMD Piledriver (2012) and newer microarchitectures 2nd gen APUs, "Trinity" (32nm), May 15, 2012 2nd gen "Bulldozer" (bdver2) with Piledriver cores, October 23, 2012 Intel Haswell (2013) and newer processors, except Pentiums and Celerons Supported commands include Note VFNMADD is result = − a · b + c, not result = − (a · b + c). VFNMSUB generates a −0 for all inputs are zero. Explicit order of operands is included in the mnemonic using numbers "132", "213", and "231": as well as operand format (packed or scalar) and size (single or double).