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Concept
Alpha 21164
Summary
The Alpha 21164, also known by its code name, EV5, is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture (ISA). It was introduced in January 1995, succeeding the Alpha 21064A as Digital's flagship microprocessor. It was succeeded by the Alpha 21264 in 1998.
First silicon of the Alpha 21164 was produced in February 1994, and the OpenVMS, Digital UNIX and Windows NT operating systems were successfully booted on it. It was sampled in late 1994 and was introduced in January 1995 at 266 MHz. A 300 MHz version was introduced in March 1995. The final Alpha 21164, a 333 MHz version, was announced on 2 October 1995, available in sample quantities. The Alpha 21164 was replaced by the Alpha 21164A as Digital's flagship microprocessor in 1996 when a 400 MHz version became available in volume quantities.
Digital used the Alpha 21164 operating at various clock frequencies in their AlphaServer servers, AlphaStation workstations. Digital also used the Alpha 21164 in their Alpha VME 5/352 and Alpha VME 5/480 single board computers and AlphaPC 164 and AlphaPC 164LX motherboards. Alpha partner Cray Research used a 300 MHz Alpha 21164 in their T3E-600 supercomputer. Third parties such as DeskStation also built workstations using the Alpha 21164.
The 21164 continued the performance lead from the 275 MHz Alpha 21064A until the introduction of the Intel Pentium Pro in November 1995, when a 200 MHz version outperformed the 300 MHz 21164 on the SPECint95_base benchmark suite. The 21164 retained its floating-point performance lead. The 333 MHz 21164 introduce the following year outperformed the Pentium Pro, but it was later surpassed by the MIPS Technologies R10000 and then by the Hewlett-Packard PA-8000 in the same year.
The Alpha 21164 is a four-issue superscalar microprocessor capable of issuing a maximum of four instructions per clock cycle to four execution units: two integer and two floating-point. The integer pipeline is seven stages long, and the floating-point pipeline is ten stages long.
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