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Concept
Netlist
Summary
In electronic design, a netlist is a description of the connectivity of an electronic circuit. In its simplest form, a netlist consists of a list of the electronic components in a circuit and a list of the nodes they are connected to. A network (net) is a collection of two or more interconnected components.
The structure, complexity and representation of netlists can vary considerably, but the fundamental purpose of every netlist is to convey connectivity information. Netlists usually provide nothing more than instances, nodes, and perhaps some attributes of the components involved. If they express much more than this, they are usually considered to be a hardware description language such as Verilog or VHDL, or one of several languages specifically designed for input to simulators or hardware compilers (such as SPICE analog simulation netlists).
Netlists can be:
Physical (based upon physical connections) or logical (based upon logical connections)
For example, connecting three components through one terminal of one of those components would be considered a direct logical connection, whereas each would be discrete physical connections.
Instance-based (clustered about a component instance) or net-based (exhaustive list of connections to a particular net)
Flat (all connections are shown) or hierarchical (connections are grouped in some way; such as which physical board or layer they are connected to. Such netlists may in addition be either folded, hiding data beneath a given level of abstraction, or unfolded, being exhaustive and thus potentially equivalent in content to flat netlists.)
Most netlists either contain or refer to descriptions of the parts or devices used. Each time a part is used in a netlist, this is called an "instance".
These descriptions will usually list the connections that are made to that kind of device, and some basic properties of that device. These connection points are called "terminals" or "pins", among several other names.
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Related publications (1)
Prediction of optically-triggered amplification in phototransistor with SPICE circuit simulators
Jean-Michel Sallese, Chiara Rossi
Modeling of optoelectronic devices involves long and complex numerical simulations, usually performed with TCAD tools. Numerical simulations provide accurate results for a single device but are not feasible when dealing with a full circuit comprising several nodes. To solve this issue, we developed a novel approach to simulate optoelectronic devices in standard SPICE circuit simulators, thus avoiding using TCAD tools. The concept is based on a coarse meshing of the semiconductor whose nodes are interconnected with the so-called Generalized Lumped Devices. The Generalized Lumped Devices are four ports devices: two ports simulate real currents and voltages in the semiconductor while two additional ports simulate excess carrier density and gradient through the definition of equivalent currents and voltages. The model behind the Generalized Devices is physics based and can correctly simulate optical generation of excess carriers, drift-diffusion transport, bulk and surface recombination as well as capacitive effects, without the need to introduce fitting or empirical parameters. Moreover, since all inputs and outputs are electrical quantities, the model is fully SPICE-compatible and can be merged with SPICE netlists of circuits. In this work, we use the Generalized Devices approach to simulate a bipolar phototransistor and prove that we can predict the photocurrent versus the collector voltage, for different illumination intensities. The model accurately takes into account the optically-triggered current amplification in the phototransistor. Sentaurus TCAD numerical simulations are in agreement with the Generalized Devices approach. Finally, since the model is physics based, we could assess the impact of different semiconductor parameters, such as doping concentrations, lifetime, surface recombination velocity, on the output characteristics of the phototransistors, directly with SPICE circuit simulators.
SPIE-INT SOC OPTICAL ENGINEERING2020Related concepts (13)
Verilog
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits. In 2009, the Verilog standard (IEEE 1364-2005) was merged into the SystemVerilog standard, creating IEEE Standard 1800-2009.
VHDL
The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gates, for design entry, documentation, and verification purposes. Since 1987, VHDL has been standardized by the Institute of Electrical and Electronics Engineers (IEEE) as IEEE Std 1076; the latest version of which is IEEE Std 1076-2019.
Netlist
In electronic design, a netlist is a description of the connectivity of an electronic circuit. In its simplest form, a netlist consists of a list of the electronic components in a circuit and a list of the nodes they are connected to. A network (net) is a collection of two or more interconnected components. The structure, complexity and representation of netlists can vary considerably, but the fundamental purpose of every netlist is to convey connectivity information.
Related courses (5)
CS-200: Computer architecture
This course completes the overview of computer architecture started at the first year.
EE-490(b): Lab in EDA based design
The goal of this lab is to get a working knowledge on the use of industrial state-of-the-art EDA (Electronic Design Automation) tools and design kits for the design of analog and digital integrated ci
EE-320: Analog IC design
Introduction to the design of analog CMOS integrated circuits at the transistor level. Understanding and design of basic structures.