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A Dual-Channel Gate Driver Design with Active Voltage Balancing Circuit for Series Connection of SiC MOSFETs

Dual-channel gate driver is commonly utilized in the industry for accommodating the widespread use of half-bridge power modules. As wide-bandgap devices become increasingly prevalent due to their superior switching characteristics compared with conventiona ...

2024

Oligolithic Cross-task Optimizations across Isolated Workloads

Anastasia Ailamaki, Eleni Zapridou, Panagiotis Sioulas

Enterprises collect data in large volumes and leverage them to drive numerous concurrent decisions and business processes. Their teams deploy multiple applications that often operate concurrently on the same data and infrastructure but have widely differen ...

2024

Emulating Multimemristive Behavior of Silicon Nanowire-Based Biosensors by Using CMOS-Based Implementations

Sandro Carrara, Junrui Chen, Kapil Bhardwaj

The research presented in this article draws inspiration from previous efforts aimed at replicating the functions of various solid-state memristors using a variety of materials. The memristor circuit emulator serves as a cost-effective tool for circuit des ...

Ieee-Inst Electrical Electronics Engineers Inc2024

EdgeAI-Aware Design of In-Memory Computing Architectures

Marco Antonio Rios

Driven by the demand for real-time processing and the need to minimize latency in AI algorithms, edge computing has experienced remarkable progress. Decision-making AI applications stand out for their heavy reliance on data-centric operations, predominantl ...

EPFL2024

Spatial Modeling for Building Design Evaluation: from Visual Landscape Quality Assessment to Devaluation Risk Estimation

Adam Robert Swietek

Zoning reform is a crucial tool for cities to adapt to contemporary challenges. However, its implementation remains challenging. Property owners, with a vested interest in the value of their neighborhoods, are sensitive to local developments and the potent ...

EPFL2024

Strategy to systematically design and deploy the ITER plasma control system: A system engineering and model-based design approach

Federico Alberto Alfredo Felici, Richard Pitts, Federico Pesamosca, Anna Ngoc Minh Trang Vu

The paper details the process of developing the ITER Plasma Control System (PCS), that is, how to design and deploy it systematically, in the most efficient and effective manner. The integrated nature of the ITER PCS, with its multitude of coupled control ...

Elsevier Science Sa2024

Modular segmentation, spatial analysis and visualization of volume electron microscopy datasets

Martin Weigert

Volume electron microscopy is the method of choice for the in situ interrogation of cellular ultrastructure at the nanometer scale, and with the increase in large raw image datasets generated, improving computational strategies for image segmentation and s ...

Nature Portfolio2024

On-Chip Fully Reconfigurable Artificial Neural Network in 16 nm FinFET for Positron Emission Tomography

Edoardo Charbon, Claudio Bruschini, Emanuele Ripiccini, Andrada Alexandra Muntean

Smarty is a fully-reconfigurable on-chip feed-forward artificial neural network (ANN) with ten integrated time-to-digital converters (TDCs) designed in a 16 nm FinFET CMOS technology node. The integration of TDCs together with an ANN aims to reduce system ...

Ieee-Inst Electrical Electronics Engineers Inc2024

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

With Moore's law coming to an end, increasingly more hope is being put in specialized hardware implemented on reconfigurable architectures such as Field-Programmable Gate Arrays (FPGAs). Yet, it is often neglected that these architectures themselves experi ...

EPFL2023

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

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Strategy to systematically design and deploy the ITER plasma control system: A system engineering and model-based design approach

Federico Alberto Alfredo Felici, Richard Pitts, Federico Pesamosca, Anna Ngoc Minh Trang Vu

Elsevier Science Sa2024

On-Chip Fully Reconfigurable Artificial Neural Network in 16 nm FinFET for Positron Emission Tomography

Edoardo Charbon, Claudio Bruschini, Emanuele Ripiccini, Andrada Alexandra Muntean

Ieee-Inst Electrical Electronics Engineers Inc2024

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Stefan Nikolic

EPFL2023