Concept

Out-of-order execution

Related publications (128)

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Hierarchical Cycle Accounting: A New Method for Application Performance Tuning

Willy Zwaenepoel, Andrzej Pawel Nowak

To address the growing difficulty of performance debugging on modern processors with increasingly complex micro-architectures, we present Hierarchical Cycle Accounting (HCA), a structured, hierarchical, architecture-agnostic methodology for the identificat ...

2015

Asynchronous memory access chaining

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber

In-memory databases rely on pointer-intensive data structures to quickly locate data in memory. A single lookup operation in such data structures often exhibits long-latency memory stalls due to dependent pointer dereferences. Hiding the memory latency by ...

2015

Accelerators for Data Processing

Yusuf Onur Koçberber

The explosive growth in digital data and its growing role in real-time analytics motivate the design of high-performance database management systems (DBMSs). Meanwhile, slowdown in supply voltage scaling has stymied improvements in core performance and ush ...

EPFL2015

Automatic generation of program execution that reaches a given failure point

George Candea, Cristian Zamfir

An execution of a target software program that causes a particular bug to manifest itself is generated. A target software program is received. A bug report generated by an execution of the target software program is received. The bug report describes a par ...

2015

Analysis and optimization of dynamic dataflow programs

Simone Casale Brunet

All computing platforms, from mobile to supercomputers, are becoming more and more heterogeneous and massively parallel. While they can provide higher power efficiency and computation throughput, effective and confident use of these systems always requires ...

EPFL2015

Confluence: unified instruction supply for scale-out servers

Babak Falsafi, Boris Robert Grot, Ilknur Cansu Kaynak

Multi-megabyte instruction working sets of server workloads defy the capacities of latency-critical instruction-supply components of a core; the instruction cache (L1-I) and the branch target buffer (BTB). Recent work has proposed dedicated prefetching tec ...

ACM Press2015

Buffer overlow vulnerabilities in CUDA: a preliminary analysis

Andrea Miele

We present a preliminary study of buffer overflow vulnerabilities in CUDA software running on GPUs. We show how an attacker can overrun a buffer to corrupt sensitive data or steer the execution flow by overwriting function pointers, e.g., manipulating the ...

Springer France2015

ADDICT: Advanced Instruction Chasing for Transactions

Anastasia Ailamaki, Pinar Tözün

Recent studies highlight that traditional transaction processing systems utilize the micro-architectural features of modern processors very poorly. L1 instruction cache and long-latency data misses dominate execution time. As a result, more than half of th ...

2014

A Primer on Hardware Prefetching

Babak Falsafi

Since the 1970’s, microprocessor-based digital platforms have been riding Moore’s law, allowing for doubling of density for the same area roughly every two years. However, whereas microprocessor fabrication has focused on increasing instruction execution r ...

Morgan & Claypool2014

Dominant speed factors of active set methods for fast MPC

Colin Neil Jones

The paper presents a review of active set (AS) algorithms that have been deployed for implementation of fast model predictive control (MPC). The main purpose of the survey is to identify the dominant features of the algorithms that contribute to fast execu ...

Wiley-Blackwell2014