Concept
Formal equivalence checking
Related publications (7)
Lateral Torsional Buckling of steel bridge girders
Jean-Paul Lebet, Raphaël Thiébaud
The Lateral Torsional Buckling (L.T.B.) design of beams in buildings has received considerable attention over the last decades, and relatively similar improved design rules are now implemented in major design standards. On the contrary, it may be shown tha ...
Structural Stability Research Council2016Imprecise Security: Quality and Complexity Tradeoffs for Hardware Information Flow Tracking
Paolo Ienne, Andrew James Becker, Ryan Charles Kastner, Wei Hu
Secure hardware design is a challenging task that goes far beyond ensuring functional correctness. Important design properties such as non-interference cannot be verified on functional circuit models due to the lack of essential information (e.g., sensitiv ...
Assoc Computing Machinery2016Approximation-aware Rewriting of AIGs for Error Tolerant Applications
Mathias Soeken, Arun Chandrasekharan
Approximation circuits offer superior performance (speed and area) compared to traditional circuits at the cost of computational accuracy. The accuracy of the results in approximation circuits is evaluated based on several error metrics such as worst-case ...
Assoc Computing Machinery2016New Data Structures and Algorithms for Logic Synthesis and Verification
The strong interaction between Electronic Design Automation (EDA) tools and Complementary Metal-Oxide Semiconductor (CMOS) technology contributed substantially to the advancement of modern digital electronics. The continuous downscaling of CMOS Field Effec ...
EPFL2015Spice Simulation of Passive Protection in Smart Power ICs
Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella
When designing in Smart Power technologies, TCAD simulations are mandatory to design effective passive protections against parasitic couplings due to minority carriers. The objective of this paper is to propose a spice-based approach to characterize electr ...
Ieee20153D Integration Technology for Lab-on-a-Chip Applications
This study adds a new dimension to lab-on-a-chip systems by employing three-dimensional (3D) integration technology for improved performance, higher functionality, and on-chip computational power. Despite the extensive amount of current research on 3D memo ...
EPFL2012Model checking: Algorithmic verification and debugging
Turing Lecture from the winners of the 2007 ACM A.M. Turing Award.In 1981, Edmund M. Clarke and E. Allen Emerson, working in the USA, and Joseph Sifakis working independently in France, authored seminal papers that founded what has become the highly succes ...
2009