Publications related to Dataflow programming

Formal Autograding in a Classroom (Experience Report)

Viktor Kuncak, Mario Bucev, Dragana Milovancevic, Samuel Chassot

We report our experience in enhancing automated grading in a functional programming course using formal verification. In our approach, we deploy a verifier for Scala programs to check equivalences between student submissions and reference solutions. Conseq ...

2024

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Dataflow programming is a methodology that enables the development of high-level, parametric programs that are independent of the underlying platform. This approach is particularly useful for heterogeneous platforms, as it eliminates the need to rewrite ap ...

SPRINGER2023

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Aurélien François Gilbert Bloch

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

EPFL2023

An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits

Andrea Guerrieri, Lana Josipovic, Carmine Rizzi

Dataflow circuits promise to overcome the scheduling limitations of standard HLS solutions. However, their performance suffers due to timing overheads caused by their handshake communication protocol. Current pipelining solutions fail to account for logic ...

New York2023

Resource Sharing in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Axel Marmet

To achieve resource-efficient hardware designs, high-level synthesis (HLS) tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed in conjunction with operation scheduling to ensure th ...

New York2023

From C/C plus plus Code to High-Performance Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Carmine Rizzi

The ability of dataflow circuits to implement dynamic scheduling promises to overcome the conservatism of static scheduling techniques that high-level synthesis tools typically rely on. Yet, the same distributed control mechanism that allows dataflow circu ...

IEEE COMPUTER SOC2022

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

The performance of programs executed on heterogeneous parallel platforms largely depends on the design choices regarding how to partition the processing on the various different processing units. In other words, it depends on the assumptions and parameters ...

MDPI2022

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Writing and optimizing application software for heterogeneous platforms including GPU units is a very difficult task that requires designer efforts and resources to consider several key elements to obtain good performance. Dataflow programming has shown to ...

2022

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Dataflow programming

Formal Autograding in a Classroom (Experience Report)

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits

Resource Sharing in Dataflow Circuits

GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors

From C/C plus plus Code to High-Performance Dataflow Circuits

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Graph Chatbot

Chat with Graph Search

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Resource Sharing in Dataflow Circuits

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

An Iterative Method for Mapping-Aware Frequency Regulation in Dataflow Circuits

GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors

From C/C plus plus Code to High-Performance Dataflow Circuits

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution

Formal Autograding in a Classroom (Experience Report)