Publications related to Die shrink

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Die shrink

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4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes

A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS

An Analog Front-End and ADC Integrated Circuit for Implantable Force and Orientation Measurements in Joint Prosthesis

On performance scaling and speed of junctionless transistors

Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

Low-power RF modeling of a 40nm CMOS technology using BSIM6

High-temperature compatible 3D-integration processes for a vacuum-sealed CNT-based NEMS

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

A CMOS Compatible Chip-to-Chip 3D Integration Platform

Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography