Concept

PCI Express

Related publications (32)

Pythia: Remote Oracles for the Masses

Remote Direct Memory Access (RDMA) is a technology that allows direct access from the network to a machine's main memory without involving its CPU. RDMA offers low-latency, high-bandwidth performance and low CPU utilization. While RDMA provides massive per ...

USENIX ASSOC2019

Hardware-conscious Hash-Joins on GPUs

Anastasia Ailamaki, Manolis Karpathiotakis, Raja Appuswamy, Periklis Chrysogelos, Panagiotis Sioulas

Traditionally, analytical database engines have used task parallelism provided by modern multisocket multicore CPUs for scaling query execution. Over the past few years, GPUs have started gaining traction as accelerators for processing analytical queries d ...

IEEE2019

An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Volkan Cevher, Cosimo Aprile, Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Thomas Toifl

This paper presents a versatile crosstalk cancellation scheme for single-ended multi-lane backplane links. System-level investigations show that a scheme, which combines analog filters and decision-feedback crosstalk compensation on the receiver (RX) side ...

2018

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

Andreas Peter Burg, Lukas Kull, Thomas Toifl, Giovanni Cherubini

The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105 orilV at a supply voltage of 0.7 V, corresponding to an energy efficiency ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

Multi-Tone Signaling and ADC-Based Digital Receiver for High-Speed Wireline Serial Links

Gain Kim

The exponential growth of Internet traffic and related demands for higher communication speed pushes processor-to-processor and processor-to-memory interconnects to provide further higher data-rate. Often time, processor-to-memory interconnectsâ speed is ...

EPFL2018

Exploring the interoperability of remote GPGPU virtualization using rCUDA and directive-based programming models

Directive-based programming models, such as OpenMP, OpenACC, and OmpSs, enable users to accelerate applications by using coprocessors with little effort. These devices offer significant computing power, but their use can introduce two problems: an increase ...

SPRINGER2018

Design Guidelines for High-Performance SCM Hierarchies

Babak Falsafi, Edouard Bugnion, Alexandros Daglis, Javier Picorel Obando, Mark Johnathon Sutherland, Dionysios Pnevmatikatos, Dmitrii Ustiugov

With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a fewfactors of DRAM. Nevertheless, the latency-sensitive nature of memory-residen ...

ACM2018

Learning-Based Hardware Design for Data Acquisition Systems

Cosimo Aprile

This multidisciplinary research work aims to investigate the optimized information extraction from signals or data volumes and to develop tailored hardware implementations that trade-off the complexity of data acquisition with that of data processing, conc ...

EPFL2018

1024-Channel Single 5W FPGA Towards High-quality Portable 3D Ultrasound Platform

Jean-Philippe Thiran, Giovanni De Micheli, Marcel Arditi, Aya Mohamed Naguib Ahmed Ibrahim, Ahmet Caner Yüzügüler

Volumetric Ultrasound (US) imaging is an emerging tech- nology for medical US applications. Typically, US imaging is 2D, where a number of vibrating elements, arranged in an array, are used to scan 2D cross-sections of the human body. In volumetric US a ma ...

2017

A Wideband MDLL with Jitter Reduction Scheme for Forwarded Clock Serial Links in 40 nm CMOS

Seyed Armin Tajalli, Yusuf Leblebici, Kiarash Gharibdoust

This paper presents the design and implementation of a multiplying delay-locked loop (MDLL) in 40 nm bulk CMOS process, which can be used as clock and data recovery (CDR) unit in source-synchronous wire-line communications. The MDLL multiplies the referenc ...

Ieee2016

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