Concept

Floorplan (microelectronics)

Related publications (14)

A Chip-Level Post-CMOS Via-Last Cu TSV Process for Multi-Layer Homogeneous 3D Integration

Seniz Esra Küçük, Yusuf Leblebici, Woo Yeong Cho

In this paper, a die-level CMOS post-processing scheme for 3D integration using the via-last approach is presented for multi-layer stacking. The process includes TSV fabrication, chip-to-chip bonding, and finally the TSV filling with Cu electroplating. The ...

Ieee2016

Substrate Current Optimization in Smart Power ICs

Pietro Buccella

Safety requirements for modern automotive electronics call for more and more robust power integrated circuits. The mixed-signal IC design flow alone is often no longer capable of tracking possible design failures in complex Smart Power integrated circuits ...

EPFL2016

Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography

Carlotta Guiducci, Yusuf Leblebici, Yüksel Temiz

This paper presents a chip-level postcomplementary metal oxide semiconductor (CMOS) processing technique for 3-D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple ...

Ieee-Inst Electrical Electronics Engineers Inc2013

A CMOS Compatible Chip-to-Chip 3D Integration Platform

Carlotta Guiducci, Michail Zervas, Yusuf Leblebici, Yüksel Temiz

In this paper, a CMOS-compatible chip-to-chip 3D integration platform will be presented. The developed technology allows reconstituting a wafer from diced and thinned chips. Then, chip-to-chip bonding and TSV fabrication steps are accomplished in wafer-lev ...

IEEE2012

3D Thermal-Aware Floorplanner for Many-Core Single-Chip Systems

David Atienza Alonso, José Luis Ayala Rodrigo

Heat removal and power density distribution delivery have become two major reliability concerns in 3D stacked technology. In this paper, we propose a thermal-driven 3D floorplanner. Our contributions include: (1) a novel multi-objective formulation to cons ...

IEEE Press2011

On the Application of a Monolithic Array for Detecting Intensity-Correlated Photons Emitted by Different Source Types

Edoardo Charbon, Dmitri Boiko

It is not widely appreciated that many subtleties are involved in the accurate measurement of intensity-correlated photons; even for the original experiments of Hanbury Brown and Twiss (HBT). Using a monolithic 4x4 array of single-photon avalanche diodes ( ...

2009

Asynchronous front-end asic for x-ray medical imaging applications implemented in CMOS 0.18μm technology

Rafal Tomasz Dlugosz

An idea as well as a CMOS implementation of the novel multi-channel readout front-end ASIC for nuclear X-ray imaging system has been presented in the paper. The circuit has been designed in an example configuration with eight equal channels, but the modula ...

2008

On-chip implementation of multiprocessor networks and switch fabrics

Giovanni De Micheli

On-chip implementation of multiprocessor systems needs to planarise the interconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor Systems on Chips (MPSoC) node processors are homogeneous, and MPSoC n ...

2008

Comparison between various types of multiple optical tweezers

René Salathé, Fabrice Merenda, Johann Rohner, Jean-Marc Fournier

Many types of optical tweezers arrays have been proposed and developed for use in conjunction with microfluidics for bio-chemical essays. Trap arrays rely on different methods allowing various degrees of flexibility and relative trapping efficiencies. Amon ...

SPIE2008

Comparison between various types of multiple optical tweezers - art. no. 70381G

René Salathé, Fabrice Merenda, Johann Rohner, Jean-Marc Fournier

Spie-Int Soc Optical Engineering, Po Box 10, Bellingham, Wa 98227-0010 Usa2008

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