Concept

Intel 8080

Related publications (9)

An Analog-Assisted Digital LDO With Single Subthreshold Output pMOS Achieving 1.44-fs FOM

This letter describes an analog-assisted digital LDO that cascades a conventional digital LDO structure with a single, large output pMOS biased in subthreshold to enable fast response to output voltage droop. By digitally controlling the gate voltage of th ...

IEEE2021

Memory Systems and Interconnects for Scale-Out Servers

Stavros Volos

The information revolution of the last decade has been fueled by the digitization of almost all human activities through a wide range of Internet services. The backbone of this information age are scale-out datacenters that need to collect, store, and proc ...

EPFL2015

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Hassan Ghasemzadeh Mohammadi

Controllable-Polarity Silicon Nanowire Transistors (CP-SiNWFETs) are among the promising candidates to complement or even replace the current CMOS technology in the near future. Polarity control is a desirable property that allows the on-line configuration ...

Institute of Electrical and Electronics Engineers2015

A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS

Yusuf Leblebici, Lukas Kull, Thomas Toifl

An asynchronous 8x interleaved redundant SAR ADC achieving 8.8GS/s at 35mW and 1V supply is presented. The ADC features pass-gate clocking for time-skew minimization and per-channel gain control based on low-power reference voltage buffers. The sub-ADC sta ...

2013

Power and pin efficient chip-to-chip communications with common-mode rejection and sso resilience

Mohammad Amin Shokrollahi, Harm Cronie

In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a spherical code, wherein a codeword is representable as a vector of a plurality ...

2012

Improving FPGA Performance for Carry-Save Arithmetic

Paolo Ienne, Philip Brisk, Ajay Kumar Verma, Hadi Parandeh Afshar

The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP applications, and further opportunities to exploit it can be exposed throug ...

2010

Oscillator Based on Suspended Gate MOS Transistors

Mihai Adrian Ionescu, Marco Mazza, Yogesh Singh Chauhan, Alexandru Rusu

The paper deals with the oscillator applications based on vibrating mode of the suspended gate SG-MOSFET transistor. In order to simulate the electrical behavior of the transistor a small-signal equivalent circuit of the gate is proposed and validated. An ...

2008

The aim of this thesis is the study of the simulation of electrically large structures and the application of the results to automotive Electromagnetic Compatibility (EMC). The theoretical and experimental work carried out has led to the development of com ...

EPFL2004

Automated Instruction-Set Extension

Paolo Ienne, Kubilay Atasu

NOVELTY - The method involves traversing a tree of potential complex computer operations; and pruning the tree for optimality under constraints. The optimality comprises maximization of a function of merit. The constraints comprise a convexity constraint, ...

2003

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