Concept
General-purpose input/output
Related publications (32)
Designed biosensors for enhanced t cell therapy
This disclosure describes a method for de novo bottom-up assembly and rational design of allosteric biosensors with programmable input-output behaviors that respond to soluble factors selectively enriched in tumors and trigger co-stimulation and cytokine s ...
2023Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems
David Atienza Alonso, Miguel Peon Quiros, Benoît Walter Denkinger
Embedded systems confront two opposite goals: low-power operation and high performance. The current trend to reach these goals is toward heterogeneous platforms, including multi-core architectures with heterogeneous cores and hardware accelerators. The lat ...
2023Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs
The pervasive adoption of field-programmable gate arrays (FPGAs) in both cyber-physical systems and the cloud has raised many security issues. Being integrated circuits, FPGAs are susceptible to fault and power side-channel attacks, which require physical ...
EPFL2023Integration of MEMS in Silicon Photonics
Like integrated electronics, integrated photonics such as Silicon Photonics benefit from increased device-density on a single chip. Silicon is an excellent material for integrated photonics because its high refractive index allows devices to be made small, ...
EPFL2021Automatic Generation of Efficient Accelerators for Reconfigurable Hardware
Christos Kozyrakis, Yunqi Zhang
Acceleration in the form of customized datapaths offer large performance and energy improvements over general purpose processors. Reconfigurable fabrics such as FPGAs are gaining popularity for use in implementing application-specific accelerators, thereby ...
Ieee2016Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance
Andreas Peter Burg, Georgios Karakonstantis, Jeremy Hugues-Felix Constantin, Anupam Chattopadhyay, Zheng Wang
This paper proposes a novel approach to modeling of gate level timing errors during high-level instruction set simulation. In contrast to conventional, purely random fault injection, our physically motivated approach directly relates to the underlying circ ...
ACM2016