The Intel 8253 and 8254 are programmable interval timers (PITs), which perform timing and counting functions using three 16-bit counters. The 825x family was primarily designed for the Intel 8080/8085-processors, but were later used in x86 compatible systems. The 825x chips, or an equivalent circuit embedded in a larger chip, are found in all IBM PC compatibles and Soviet computers like the Vector-06C. In PC compatibles, Timer Channel 0 is assigned to IRQ-0 (the highest priority hardware interrupt). Timer Channel 1 is assigned to DRAM refresh (at least in early models before the 80386). Timer Channel 2 is assigned to the PC speaker. The Intel 82c54 (c for CMOS logic) variant handles up to 10 MHz clock signals. The 8253 is described in the 1980 Intel "Component Data Catalog" publication. The 8254, described as a superset of the 8253 with higher clock speed ratings, has a "preliminary" data sheet in the 1982 Intel "Component Data Catalog". The 8254 is implemented in HMOS and has a "Read Back" command not available on the 8253, and permits reading and writing of the same counter to be interleaved. Modern PC compatibles, either when using SoC CPUs or southbridge typically implement full 8254 compatibility for backward compatibility and interoperability. The Read Back command being a vital I/O feature for interoperability with multicore CPUs and GPUs. There is military version of Intel M8253 with the temperature range of -55 °C to +125 °C which it also have ±10% 5V power tolerance. The available 82C53 CMOS version was outsourced to Oki Electronic Industry Co., Ltd. The available package version of Intel 82C54 was in 28-pin PLCC of sampling at first quarter of 1986. The timer has three counters, numbered 0 to 2. Each channel can be programmed to operate in one of six modes. Once programmed, the channels operate independently. Each counter has two input pins – "CLK" (clock input) and "GATE" – and one pin, "OUT", for data output. The three counters are 16-bit down counters independent of each other, and can be easily read by the CPU.