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Related publications (14)
Micro-architectural Analysis of OLAP: Limitations and Opportunities
Anastasia Ailamaki, Utku Sirin
Understanding micro-architectural behavior is important for efficiently using hardware resources. Recent work has shown that in-memory online transaction processing (OLTP) systems severely underutilize their core micro-architecture resources [29]. Whereas, ...
ASSOC COMPUTING MACHINERY2020Automatic Application of Power Analysis Countermeasures
Paolo Ienne, Francesco Regazzoni, Philip Brisk, David Novo Bruna, Ali Galip Bayrak
We introduce a compiler that automatically inserts software countermeasures to protect cryptographic algorithms against power-based side-channel attacks. The compiler first estimates which instruction instances leak the most information through side-channe ...
Institute of Electrical and Electronics Engineers2015Synchrotron X Ray Induced Axonal Transections in the Brain of Rats Assessed by High-Field Diffusion Tensor Imaging Tractography
Since approximately two thirds of epileptic patients are non-eligible for surgery, local axonal fiber transections might be of particular interest for them. Micrometer to millimeter wide synchrotron-generated X-ray beamlets produced by spatial fractionatio ...
Public Library Science2014Making Wide-Issue VLIW Processors Viable on FPGAs
Paolo Ienne, Madhura Purnaprajna
Soft and highly-customized processors are emerging as a common way to efficiently control large amount of computing resources available on FPGAs. Yet, some processor architectures of choice for DSP and media applications, such as wide-issue VLIW processors ...
2012Neural Network based On-Chip Thermal Simulator
David Atienza Alonso, Pratyush Kumar
With increasing power densities, runtime thermal management is becoming a necessity in today’s systems, especially so for highly integrated Multi-Processor Systems-on-Chip (MPSoCs). In this paper, we propose a neural network (NN) based approach to implemen ...
IEEE Press2010Joint Hardware-Software Leakage Minimization Approach for the Register File of VLIW Embedded Architectures
Giovanni De Micheli, David Atienza Alonso, José Luis Ayala Rodrigo
New applications demand very high processing power when run on embedded systems. Very Long Instruction Word (VLIW) architectures have emerged as a promising alternative to provide such processing capabilities under the given energy budget. However, in this ...
2008Thermal Characterization and Thermal Management in Processor-Based Systems
The register file is one of the hottest devices in processor- based systems. Leakage reduction techniques and DTM mechanisms re- quire a thermal characterization of the hardware. This paper presents a thermal model to analyze the temperature evolution in t ...
2007Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems
David Atienza Alonso, José Luis Ayala Rodrigo
This paper presents a thermal model to analyze the temperature evolution in the shared register files found on VLIW systems. The use of this model allows the analysis of several factors that have an strong impact on the heat transfer: layout topology, plac ...
IEEE Computer Society2007Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors
Giovanni De Micheli, David Atienza Alonso, José Luis Ayala Rodrigo
Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various speeds. In this paper we present a complete approach that handles speed varia ...
2007Optimal Loop-Unrolling Mechanisms and Architectural Extensions for an Energy-Efficient Design of Shared Register Files in MPSoCs
David Atienza Alonso, José Luis Ayala Rodrigo, Roman Hermida Correa
In this paper we introduce a new hardware/software approach to reduce the energy of the shared register file in upcoming embedded architectures with several VLIW processors. This work includes a set of architectural extensions and special loop unrolling te ...
IEEE Press2005