Processor power dissipation | EPFL Graph Search

Processor power dissipation or processing unit power dissipation is the process in which computer processors consume electrical energy, and dissipate this energy in the form of heat due to the resistance in the electronic circuits. Power management Variable TDP Designing CPUs that perform tasks efficiently without overheating is a major consideration of nearly all CPU manufacturers to date. Historically, early CPUs implemented with vacuum tubes consumed power on the order of many kilowatts. Current CPUs in general-purpose personal computers, such as desktops and laptops, consume power in the order of tens to hundreds of watts. Some other CPU implementations use very little power; for example, the CPUs in mobile phones often use just a few watts of electricity, while some microcontrollers used in embedded systems may consume only a few milliwatts or even as little as a few microwatts. There are a number of engineering reasons for this pattern:

For a given CPU core, energy

High-Speed Wireline Link Design

Hazar Yüksel

High-speed serial links are a crucial application of semiconductor technology and have been the enabler of the scaling of computing systems. The increasing data-rate requirements of these links have only been partially satisfied by advancements in process technologies. Implementing serial links operating at a data rate of more than 25 Gb/s thus requires constantly inventing smarter algorithms, architectures, power-management techniques, and new standards. The Viterbi algorithm (VA), an attractive solution for symbol detection in the presence of intersymbol interference (ISI) and noise, minimizes the error probability in detecting the whole symbol sequence, instead of a single symbol as in decision-feedback equalization. The bit-error-rate (BER) performance of the VA is thus better than that of symbol-by-symbol detectors because the VA does not cancel the ISI, but rather uses the information embedded therein to maximize the reliability of its decisions. However, implementing a maximum-likelihood sequence detector (MLSD) realizing the VA may be prohibitive because design specifications regarding area, latency, power consumption, and speed may not be satisfied concurrently. Suboptimal solutions, such as feed-forward and decision-feedback equalizers (DFEs), may therefore be chosen instead of MLSDs due to their lower implementation complexity. A reduced-state sequence detector (RSSD) reduces the implementation complexity of the MLSD with negligible performance degradation by exploiting set-partitioning principles and embedded per-survivor decision feedback. A sliding-block or systolic-array Viterbi detector (VD) breaks the speed bottleneck in sequence-detector implementations by parallelizing the operation of the VA. In this thesis, we implement a 56-Gb/s four-level pulse-amplitude-modulation (4-PAM) DFE to demonstrate the feasibility of a multi-level analog-to-digital-converter (ADC)-based symbol-by-symbol detector in terms of achievable area, BER, energy-efficiency, latency, and speed figures comparable to those of analog solutions. Furthermore, to improve the BER figures, we implement a 25.6-Gb/s 4-PAM reduced-state sliding-block VD to demonstrate the feasibility of a multi-level sequence detector in terms of achievable area, energy-efficiency, latency, and speed figures comparable to those of symbol-by-symbol detectors. Moreover, we develop a sliding-block VA with optimized unequal synchronization and survivor path memory lengths to reduce its implementation complexity, latency, and power consumption. An increase in speed is thereby achieved at the same implementation complexity, BER, latency, and power consumption. We then develop a novel VD with embedded per-survivor decision feedback, whose longest path contains only one adder, to increase its speed significantly. Next, we propose a concatenated-coding scheme using an outer Reed—Solomon code and a four-dimensional (4-D) 5-PAM inner trellis-coded-modulation (TCM) scheme to achieve signal-to-noise-ratio gains without bandwidth expansion. Finally, we implement a 70-Gb/s 4-D 5-PAM systolic-array TCM decoder with eight states, which includes an inverse Tomlinson—Harashima precoder, to demonstrate the feasibility of a multi-level ADC-based sequence decoder in terms of achievable speed figures comparable to those of sequence detectors.

EPFL2017

Asynchronous front-end asic for x-ray medical imaging applications implemented in CMOS 0.18μm technology

Rafal Tomasz Dlugosz

An idea as well as a CMOS implementation of the novel multi-channel readout front-end ASIC for nuclear X-ray imaging system has been presented in the paper. The circuit has been designed in an example configuration with eight equal channels, but the modular structure enables an easy realization of larger systems with even hundreds of channels. Various new circuit solutions have been proposed by author and used in the circuit, such as: an asynchronous output multiplexer, a pulse shaper and a peak detector with a built-in clock generator, which activates the circuit only in the situation when a new impulse occurs at the input. This technique allows for very low power dissipation. In the worst case scenario, i.e. when all channels would be active at the same time, the power dissipation is kept below 2 mW. By introducing an efficient RESET mechanism that turns off a given channel just after reading out the information, the counting rate of a single channel has been increased to about 3 MSps. The proposed circuit solutions allow for a very low chip area usage that for a single channel is equal to 0.021 mm2, while the total chip area is equal to 0.17 mm2.

2008

Current-Mode Analog Adaptive Mechanism for Ultralow-Power Neural Networks

Rafal Tomasz Dlugosz

Neural networks (NNs) implemented at the transistor level are powerful adaptive systems. They can perform hundreds of operations in parallel but at the expense of a large number of building blocks. In the case of analog realization, an extremely low chip area and low power dissipation can be achieved. To accomplish this, the building blocks should be simple. This brief presents a new current-mode low-complexity flexible adaptive mechanism (ADM) with a strongly reduced leakage in analog memory. Input signals ranging from 0.5 to 20 μA are held for 10–50 ms, with the leakage rate from 0.2%/ms to 0.04%/ms, respectively, depending on temperature. A small storage capacitor of 200 fF enables a short write time (< 100 ns). A single ADMcell occupies 1400 μm2 when realized in the Taiwan Semiconductor Manufacturing Company Ltd. CMOS 0.18-μm technology. The potential application of this NN is envisioned in a mobile platform based on a wireless sensor network to be used for online analysis of electrocardiography signals.

Institute of Electrical and Electronics Engineers2011

High-Speed Wireline Link Design

Hazar Yüksel

EPFL2017