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Related publications (10)

A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time

Side-channel CPU disassembly is a side-channel attack that allows an adversary to recover instructions executed by a processor. Not only does such an attack compromise code confidentiality, it can also reveal critical information on the system’s internals. ...

2022

Prediction of optically-triggered amplification in phototransistor with SPICE circuit simulators

Jean-Michel Sallese, Chiara Rossi

Modeling of optoelectronic devices involves long and complex numerical simulations, usually performed with TCAD tools. Numerical simulations provide accurate results for a single device but are not feasible when dealing with a full circuit comprising sever ...

SPIE-INT SOC OPTICAL ENGINEERING2020

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Edouard Giacomin

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can ...

2018

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Xifan Tang

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two ...

EPFL2017

Today's rapid advances in the physical implementation of quantum computers demand for scalable synthesis methods in order to map practical logic designs to quantum architectures. We present a synthesis algorithm for quantum computing based on k-LUT network ...

IEEE2017

Substrate Current Optimization in Smart Power ICs

Pietro Buccella

Safety requirements for modern automotive electronics call for more and more robust power integrated circuits. The mixed-signal IC design flow alone is often no longer capable of tracking possible design failures in complex Smart Power integrated circuits ...

EPFL2016

Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

In this paper, we present biconditional binary deci- sion diagrams (BBDDs), a novel canonical representation form for Boolean functions. BBDDs are binary decision diagrams where the branching condition, and its associated logic expansion, is biconditional ...

2014

Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistors

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Jian Zhang, Shashi Kanth Bobba, Michele De Marchi

Ambipolar transistors with on-line configurability to n-type and p-type polarity are desirable for future integrated circuits. Regular logic tiles have been recognized as an efficient layout fabric for ambipolar devices. In this work, we present a process/ ...

2012

Delay Optimum And Area Optimal Mapping Of k-LUT Based FPGA Circuits

The paper presents several improvements to our synthesis platform Xsynth that was developed targeting advanced logic synthesis and technological mapping for k-LUT based FPGAs. Having implemented an efficient exhaustive k-feasible cone generator it was targ ...

2009

Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used ...

2009

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