Publications related to Parallel programming model

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Ayatallah Ahmed Gamal Kamal Elakhras

High-level synthesis (HLS) is the process of automatically generating circuits out of high-level language descriptions. Previous research has shown that dynamically scheduled HLS through elastic circuit generation is successful at exploiting parallelism in ...

IEEE COMPUTER SOC2022

Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Developing and fine-tuning software programs for heterogeneous hardware such as CPU/GPU processing platforms comprise a highly complex endeavor that demands considerable time and effort of software engineers and requires evaluating various fundamental comp ...

MDPI2022

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Writing and optimizing application software for heterogeneous platforms including GPU units is a very difficult task that requires designer efforts and resources to consider several key elements to obtain good performance. Dataflow programming has shown to ...

2022

Proof of Multi-Stage Programming with Generative and Analytical Macros

Martin Odersky, Nicolas Alexander Stucki, Jonathan Immanuel Brachthäuser

In metaprogramming, code generation and code analysis are complementary. Traditionally, principled metaprogramming extensions for programming languages, like MetaML and BER MetaOCaml, offer strong foundations for code generation but lack equivalent support ...

EPFL2021

Fully-Asynchronous Fully-Implicit Variable-Order Variable-Timestep Simulation of Neural Networks

Felix Schürmann, Michael Lee Hines, Bruno Ricardo Da Cunha Magalhães

State-of-the-art simulations of detailed neurons follow the Bulk Synchronous Parallel execution model. Execution is divided in equidistant communication intervals, with parallel neurons interpolation and collective communication guiding synchronization. Su ...

2020

Manycore clique enumeration with fast set intersections

Paolo Ienne, Kubilay Atasu, Radu Ioan Stoica, Jovan Blanusa

Listing all maximal cliques of a given graph has important applications in the analysis of social and biological networks. Parallelisation of maximal clique enumeration (MCE) algorithms on modern manycore processors is challenging due to the task-level par ...

ACM2020

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Mirjana Stojilovic, Philip Brisk, Frédéric Gessler

RePlAce is a state-of-the-art prototype of a flat, analytic, and nonlinear global cell placement algorithm, which models a placement instance as an electrostatic system with positively charged objects. It can handle large-scale standard-cell and mixed-cell ...

IEEE2020

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, William Andrew Simon

Hybrid caches consisting of both SRAM and emerging Non-Volatile Random Access Memory (eNVRAM) bitcells increase cache capacity and reduce power consumption by taking advantage of eNVRAM's small area footprint and low leakage energy. However, they also inhe ...

2020

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Parallel programming model

Dynamic power budget redistribution under a power cap on multi-application environments

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery

Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Proof of Multi-Stage Programming with Generative and Analytical Macros

Fully-Asynchronous Fully-Implicit Variable-Order Variable-Timestep Simulation of Neural Networks

Manycore clique enumeration with fast set intersections

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

PokeME: Applying Context-Driven Notifications to Increase Worker Engagement in Mobile Crowd-Sourcing

Graph Chatbot

Chat with Graph Search

Dynamic power budget redistribution under a power cap on multi-application environments

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

Unleashing Parallelism in Elastic Circuits with Faster Token Delivery

PokeME: Applying Context-Driven Notifications to Increase Worker Engagement in Mobile Crowd-Sourcing

Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Manycore clique enumeration with fast set intersections

Proof of Multi-Stage Programming with Generative and Analytical Macros

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Fully-Asynchronous Fully-Implicit Variable-Order Variable-Timestep Simulation of Neural Networks