Publications related to Instruction-level parallelism

POSEIDON: Privacy-Preserving Federated Neural Network Learning

Jean-Pierre Hubaux, Juan Ramón Troncoso-Pastoriza, Jean-Philippe Léonard Bossuat, Apostolos Pyrgelis, David Jules Froelicher, Joao André Gomes de Sá e Sousa, Sinem Sav

In this paper, we address the problem of privacy-preserving training and evaluation of neural networks in an N-party, federated learning setting. We propose a novel system, POSEIDON, the first of its kind in the regime of privacy-preserving neural network ...

INTERNET SOC2021

Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs

Marco Mattavelli, Simone Casale Brunet, Endri Bezati, Anatoly Prihozhy

Large dataflow designs are a result of behavioral specification of modern complex digital systems and/or a result of unfolding and transforming looped and branched programs. Since deep-submicron silicon technology provides large amounts of available resour ...

SPRINGER2020

SpecROP: Speculative Exploitation of ROP Chains

Mathias Josef Payer, Atri Bhattacharyya, Andrés Sánchez Marín

Speculative execution attacks, such as Spectre, reuse code from the victim’s binary to access and leak secret information during speculative execution. Every variant of the attack requires very particular code sequences, necessitating elaborate gadget-sear ...

2020

Manycore clique enumeration with fast set intersections

Paolo Ienne, Kubilay Atasu, Radu Ioan Stoica, Jovan Blanusa

Listing all maximal cliques of a given graph has important applications in the analysis of social and biological networks. Parallelisation of maximal clique enumeration (MCE) algorithms on modern manycore processors is challenging due to the task-level par ...

ACM2020

Speculative Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

With FPGAs facing broader application domains, the conversion of imperative languages into dataflow circuits has been recently revamped as a way to overcome the conservatism of statically scheduled high-level synthesis. Apart from the ability to extract pa ...

ASSOC COMPUTING MACHINERY2019

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

Paolo Ienne, Mikhail Asiatici

FPGAs rely on massive datapath parallelism to accelerate applications even with a low clock frequency. However, applications such as sparse linear algebra and graph analytics have their throughput limited by irregular accesses to external memory for which ...

ASSOC COMPUTING MACHINERY2019

An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, William Andrew Simon

With the spread of cloud services and Internet of Things concept, there is a popularization of machine learning and artificial intelligence based analytics in our everyday life. However, an efficient deployment of these data-intensive services requires per ...

2019

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Atri Bhattacharyya

When applications have unpredictable memory accesses or irregular control flow, dataflow circuits overcome the limitations of statically scheduled high-level synthesis (HLS). If memory dependences cannot be determined at compile time, dataflow circuits rel ...

IEEE COMPUTER SOC2019

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Instruction-level parallelism

POSEIDON: Privacy-Preserving Federated Neural Network Learning

Diablo: A Distributed Analytical Blockchain Benchmark Framework Focusing on Real-World Workloads

Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs

SpecROP: Speculative Exploitation of ROP Chains

Manycore clique enumeration with fast set intersections

Speculative Dataflow Circuits

Asynchronous Branch-Paralle Simulation of Detailed Neuron Models

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Graph Chatbot

Chat with Graph Search

Speculative Dataflow Circuits

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

SpecROP: Speculative Exploitation of ROP Chains

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

Asynchronous Branch-Paralle Simulation of Detailed Neuron Models

POSEIDON: Privacy-Preserving Federated Neural Network Learning

Pipeline Synthesis and Optimization from Branched Feedback Dataflow Programs

Diablo: A Distributed Analytical Blockchain Benchmark Framework Focusing on Real-World Workloads

Manycore clique enumeration with fast set intersections

An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication