Publications related to SystemVerilog

Analytic modelling of passive microfluidic mixers

Jean-Michel Sallese, Christophe Lallement

This paper deals with a new analytical model for microfluidic passive mixers. Two common approaches already exist for such a purpose. On the one hand, the resolution of the advection-diffusion-reaction equation (ADRE) is the first one and the closest to ph ...

AMER INST MATHEMATICAL SCIENCES-AIMS2022

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Paolo Ienne, Grace Zgheib, Stefan Nikolic

Technology scaling makes metal delay ever more problematic, but routing between Look-Up Tables (LUTs) still passes through a series of transistors. It seems wise to avoid the corresponding delay whenever possible. Direct connections between LUTs, both with ...

ASSOC COMPUTING MACHINERY2020

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Edouard Giacomin

In this paper, we developed a simulation-based architecture evaluation framework for field-programmable gate arrays (FPGAs), called FPGA-SPICE, which enables automatic layout-level estimation and electrical simulations of FPGA architectures. FPGA-SPICE can ...

2018

System Level simulation framework for the ASICs development of a novel particle physics detector

Yusuf Leblebici, Alessandro Caratelli, Davide Ceresa, Simone Scarfì

The simulation of the passage of particles through matter using Monte Carlo methods is broadly used in the development of particle detectors for high energy physics experiments. To develop the readout electronics for the Compact Muon Solenoid (CMS) experim ...

IEEE2018

Post-P&R Performance and Power Analysis for RRAM-based FPGAs

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Edouard Giacomin

Resistive Random Access Memory (RRAM)-based FPGAs are predicted to outperform conventional FPGAs architectures in area, delay and power over a wide range of voltage operations, allowing novel energy-quality trade-offs for reconfigurable computing. The oppo ...

2018

Virtual Prototyping Methodology for Power Automation Cyber-Physical-Systems

Juan Sebastian Rodriguez Estupinan

In this thesis, the author proposes a circular system development model which considers all the stages in a typical development process for industrial systems. In particular, the present work shows that the use of virtual prototyping at early stages of the ...

EPFL2017

Hierarchical Reversible Logic Synthesis Using LUTs

Giovanni De Micheli, Mathias Soeken

Today's rapid advances in the physical implementation of quantum computers demand for scalable synthesis methods in order to map practical logic designs to quantum architectures. We present a synthesis algorithm for quantum computing based on k-LUT network ...

IEEE2017

Functional BIP: Embedding connectors in functional programming languages

Romain Edelmann, Joseph Sifakis, Simon Bliudze

This paper presents a theoretical foundation for functional language implementations of Behaviour–Interaction–Priority (BIP). We introduce a set of connector combinators describing synchronisation, data transfer, priorities and dynamicity in a principled w ...

Elsevier Science Inc2017

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SystemVerilog

Analytic modelling of passive microfluidic mixers

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

CASSIS: Characterization with Adaptive Sample-Size Inferential Statistics Applied to Inexact Circuits

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

System Level simulation framework for the ASICs development of a novel particle physics detector

Post-P&R Performance and Power Analysis for RRAM-based FPGAs

Virtual Prototyping Methodology for Power Automation Cyber-Physical-Systems

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Hierarchical Reversible Logic Synthesis Using LUTs

Functional BIP: Embedding connectors in functional programming languages

Graph Chatbot

Chat with Graph Search

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs

CASSIS: Characterization with Adaptive Sample-Size Inferential Statistics Applied to Inexact Circuits

Virtual Prototyping Methodology for Power Automation Cyber-Physical-Systems

System Level simulation framework for the ASICs development of a novel particle physics detector

Functional BIP: Embedding connectors in functional programming languages

Analytic modelling of passive microfluidic mixers

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Post-P&R Performance and Power Analysis for RRAM-based FPGAs

Circuit Design, Architecture and CAD for RRAM-based FPGAs

Hierarchical Reversible Logic Synthesis Using LUTs