Publications related to Static timing analysis

Low-Latency High-Bandwidth Circuit and System Design for Trigger Systems in High Energy Physics

The increasing luminosity in HEP (High Energy Physics) colliders demands trigger systems to be more selective. First, more information from the detector is routed to the trigger system. Second, larger parts of this information are processed together. These ...

EPFL2021

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits

Giovanni De Micheli, Eleonora Testa, Heinz Riener, Siang-Yun Lee

Adiabatic quantum-flux-parametron (AQFP) circuits are a family of superconducting electronic (SCE) circuits that have recently gained growing interest due to their low-energy consumption, and may serve as alternative technology to overcome the down-scalin ...

Association for Computing Machinery2021

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultra-Low Power Processors

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Miguel Peon Quiros, Ruben Braojos Lopez, Loris Gérard Duch

Aging effects in digital circuits change the switching characteristics of their transistors, resulting in timing violations that can lead to functional errors at the system level. In particular, BTI is a degradation effect that changes the threshold voltag ...

2020

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors

David Atienza Alonso, Alexandre Sébastien Julien Levisse, Miguel Peon Quiros, Ruben Braojos Lopez, Loris Gérard Duch

Aging effects in digital circuits change the switching characteristics of their transistors, resulting in timing violations that can lead to functional errors at the system level. In particular, bias temperature instability (BTI) is a degradation effect th ...

2020

A Sensor Fusion Approach to the Estimation of Instantaneous Velocity Using Single Wearable Sensor During Sprint

Kamiar Aminian, Frédéric Meyer, Salil Apte, Farzin Dadashi, Vincent Gremeaux

Power-Force-Velocity profile obtained during a sprint test is crucial for designing personalized training and evaluating injury risks. Estimation of instantaneous velocity is requisite for developing these profiles and the predominant method for this estim ...

2020

Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?

Francesco Regazzoni, Mirjana Stojilovic, Louis Coulon, Ognjen Glamocanin

Recent works have demonstrated the possibility of extracting secrets from a cryptographic core running on an FPGA by means of remote power analysis attacks. To mount these attacks, an adversary implements a voltage fluctuation sensor in the FPGA logic, rec ...

2020

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to conventional SRAM due to its high-density, low-leakage, and inherent two-ported functionality. However, its dynamic storage mechanism requires power-hungry refresh cycles to maintain data. ...

IEEE2020

FirmFuzz: Automated IoT Firmware Introspection and Analysis

Mathias Josef Payer, Hui Peng

While the number of IoT devices grows at an exhilarating pace their security remains stagnant. Imposing secure coding standards across all vendors is infeasible. Testing individual devices allows an analyst to evaluate their security post deployment. Any d ...

ASSOC COMPUTING MACHINERY2019

A Magnet-Based Timing System to Detect Gate Crossings in Alpine Ski Racing

Kamiar Aminian, Benedikt Fasel

In alpine skiing, intermediate times are usually measured with photocells. However, for practical reasons, the number of intermediate cells is limited to three⁻four, making a detailed timing analysis difficult. In this paper, we propose and validate a magn ...

2019

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Gain-cell embedded DRAM (GC-eDRAM) is an attractive alternative to conventional SRAM due to its high-density, low-leakage, and inherent two-ported functionality. However, its dynamic storage mechanism requires power-hungry refresh cycles to maintain data. ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Static timing analysis

Low-Latency High-Bandwidth Circuit and System Design for Trigger Systems in High Energy Physics

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultra-Low Power Processors

Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors

A Sensor Fusion Approach to the Estimation of Instantaneous Velocity Using Single Wearable Sensor During Sprint

Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

FirmFuzz: Automated IoT Firmware Introspection and Analysis

A Magnet-Based Timing System to Detect Gate Crossings in Alpine Ski Racing

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

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Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits

Low-Latency High-Bandwidth Circuit and System Design for Trigger Systems in High Energy Physics

A Sensor Fusion Approach to the Estimation of Instantaneous Velocity Using Single Wearable Sensor During Sprint

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

A Magnet-Based Timing System to Detect Gate Crossings in Alpine Ski Racing

Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

FirmFuzz: Automated IoT Firmware Introspection and Analysis