Publications related to Bitwise operation

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

David Atienza Alonso, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, Flavio Ponzina

By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional o ...

2023

Indexing Protected Deep Face Templates by Frequent Binary Patterns

Sébastien Marcel, Hatef Otroshi Shahreza

In this work, we present a simple biometric indexing scheme which is binning and retrieving cancelable deep face templates based on frequent binary patterns. The simplicity of the proposed approach makes it applicable to unprotected as well as protected, i ...

IEEE2022

MeshUDF: Fast and Differentiable Meshing of Unsigned Distance Field Networks

Pascal Fua, Benoît Alain René Guillard, Federico Stella

Unsigned Distance Fields (UDFs) can be used to represent non-watertight surfaces. However, current approaches to converting them into explicit meshes tend to either be expensive or to degrade the accuracy. Here, we extend the marching cube algorithm to han ...

2022

Programmable Logic Gates Based On Tunable Multistable Mechanisms

Simon Nessim Henein, Hubert Pierre-Marie Benoît Schneegans, Ilan Vardi, Mohamed Gamal Abdelrahman Ahmed Zanaty

Binary logic operations are the building blocks of computing machines. In this paper, we present a new programmable binary logic gate based on programmable multistable mechanisms (PMM), which are multistable structures whose stability behavior depends on m ...

AMER SOC MECHANICAL ENGINEERS2020

Blade: An in-Cache Computing Architecture for Edge Devices

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, William Andrew Simon, Yasir Mahmood Qureshi

Area and power constrained edge devices are increasingly utilized to perform compute intensive workloads, necessitating increasingly area and power efficient accelerators. In this context, in-SRAM computing performs hundreds of parallel operations on spati ...

2020

Reconfigurable logic circuit

Edoardo Charbon, Francesco Regazzoni

The present invention relates to a reconfigurable logic circuit comprising - a first, second and third switching circuit arranged for receiving a first input bit, a second input bit and a third input bit, respectively, and each arranged for being configure ...

2020

Structural Rewriting in XOR-Majority Graphs

Giovanni De Micheli, Mathias Soeken, Zhufei Chu

In this paper, we present a structural rewriting method for a recently proposed XOR-Majority graph (XMG), which has exclusive-OR (XOR), majority-of-three (MAJ), and inverters as primitives. XMGs are an extension of Majority-Inverter Graphs (MIGs). Previous ...

ASSOC COMPUTING MACHINERY2019

A Fast, Reliable and Wide-voltage-range In-memory Computing Architecture

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, William Andrew Simon

In-Memory Computing (IMC) solutions, and particularly bitline computing in SRAM, appear promising as they mitigate one of the most energy consuming aspects in computation: data movement. In this work we propose a fast (2.4Ghz for bitwise operations and 2.4 ...

Association for Computing Machinery2019

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Bitwise operation

EdgeAI-Aware Design of In-Memory Computing Architectures

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

Indexing Protected Deep Face Templates by Frequent Binary Patterns

MeshUDF: Fast and Differentiable Meshing of Unsigned Distance Field Networks

Programmable Logic Gates Based On Tunable Multistable Mechanisms

Blade: An in-Cache Computing Architecture for Edge Devices

Reconfigurable logic circuit

Structural Rewriting in XOR-Majority Graphs

A Fast, Reliable and Wide-voltage-range In-memory Computing Architecture

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

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Chat with Graph Search

Reconfigurable logic circuit

Structural Rewriting in XOR-Majority Graphs

A Fast, Reliable and Wide-voltage-range In-memory Computing Architecture

Programmable Logic Gates Based On Tunable Multistable Mechanisms

Indexing Protected Deep Face Templates by Frequent Binary Patterns

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

EdgeAI-Aware Design of In-Memory Computing Architectures

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference

Blade: An in-Cache Computing Architecture for Edge Devices

MeshUDF: Fast and Differentiable Meshing of Unsigned Distance Field Networks