Juan Ramón Troncoso-PastorizaJuan Ramón Troncoso-Pastoriza received the M.S. degree in Telecommunications Engineering (Hons) from the University of Vigo, Vigo, Spain, in 2005, when he also received the Best Student Award from the Galician Government and the National Best Graduate Student Award from the Spanish Ministry of Education and Science. He held two consecutive grants from the Spanish Ministry of Education and Science for collaboration with the Telematics Department (2004-2005) and for the development of the Ph.D. Thesis (Formación de Profesorado Universitario, 2006-2011). In 2012, he received the Ph.D. in Telecommunications Engineering (European Doctorate Mention, Hons). His Ph.D. thesis, entitled "Encrypted Domain Processing for Signal Processing Applications," was awarded the Best Ph.D. Thesis by the University of Vigo, and the best Ph.D. Thesis in Spain in Telecommunication Networks and Services by the Spanish Official Institute of Telecommunications Engineers (COIT).
He worked at the Signal Theory and Communications Department in the University of Vigo from 2005 to 2016 as an Associate Researcher, and as a Post-doctoral Researcher at AtlanTTic Research Center for Information and Communication Technologies at the University of Vigo since 2012. Between 2006 and 2007 he visited the Information and Systems Security Department at Philips Research Europe (The Netherlands), where he started working on genomic privacy and filed a PCT international patent application. In 2016, he joined the Laboratory for Communications and Applications 1 at the École Polytechnique Fédérale de Lausanne, Switzerland, as a Post-doctoral researcher to work in genomic privacy-related topics.
He is an elected member of the IEEE Information Forensics and Security Technical Committee and the IEEE Signal Processing Society Student Services Committee for the period 2017-2019. He has been a member of the Technical Program Committee of the IEEE WIFS 2015 and 2017, and part of the organizing committees of IEEE WIFS 2012, ACM IH&MMSEC 2016 and the upcoming EUSIPCO 2018. He has also taken part in several European projects in the area of multimedia security, such as ECRYPT and SPEED, both in FP6; during 2015-2018 he has been the scientific coordinator of the EU H2020 funded project WITDOM, focused on privacy-preserving computation in Cloud. He currently participates in several Swiss projects related to medical privacy and security (DPPH), and application of distributed ledger technologies. He has been reviewer of more than 20 peer-reviewed international journals and more than 30 editions of several international conferences in the field of information security, and serves now as Associate Editor of Elsevier's Digital Signal Processing Journal, EURASIP Journal on Information Security, EURASIP Journal of Visual Communications and Image Representation, and IET Information Security.
He has also participated in several National and regional public-funded projects and private contracts related to information security and privacy protection, an area in which he has coauthored numerous papers in international journals and conferences, and holds four granted international patents in collaboration with Gradiant (Galician Research Center in Advanced Telecommunications).
His past teaching experience covers several undergraduate courses on Communications Theory and Digital Communications in Telecommunications Engineering Bachelor and 5-year degrees at the University of Vigo, and the supervision of multiple semester and master students at EPFL. Additionally, he worked as the network manager and webmaster of the Signal Processing in Communications Group at the University of Vigo from 2009 to 2016, and was the webmaster for the IEEE WIFS 2012.
His research interests include genomic privacy, secure signal processing, applied cryptography for privacy protection and multimedia security.
Paolo IennePaolo Ienne has been a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, he worked for the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG) where he was at the head of the Embedded Memories unit in the Design Libraries division. His research interests include various aspects of computer and processor architecture, FPGAs and reconfigurable computing, electronic design automation, and computer arithmetic. Ienne was a recipient of Best Paper Awards at the 20th, 24th, and 28th ACM/SIGDA International Symposia on Field-Programmable Gate Arrays (FPGA), in 2012, 2016 and 2020, at the 19th and 30th International Conference on Field-Programmable Logic and Applications (FPL), in 2009 and 2020, at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), in 2007, and at the 40th Design Automation Conference (DAC), in 2003; many other papers have been candidates to Best Paper Awards in prestigious venues. He has served as general, programme, and topic chair of renown international conferences, including organizing in Lausanne the 26th International Conference on Field-Programmable Logic and Applications (FPL) in 2016. He serves on the steering committee of the IEEE Symposium on Computer Arithmetic (ARITH) and of the International Conference on Field-Programmable Logic and Applications (FPL). Ienne has guest edited a number of special issues and special sections on various topics for IEEE and ACM journals. He is regularly member of program committees of international workshops and conferences in the areas of design automation, computer architecture, embedded systems, compilers, FPGAs, and asynchronous design. He has been an associate editor of ACM Transactions on Architecture and Code Optimization (TACO), since 2015, of ACM Computing Surveys (CSUR), since 2014, and of ACM Transactions on Design Automation of Electronic Systems (TODAES) from 2011 to 2016.
Alessandro ChiesaAlessandro Chiesa is a faculty member in computer science. He conducts research in complexity theory, cryptography, and security, with a focus on the theoretical foundations and practical implementations of cryptographic proofs that are short and easy to verify. He is a co-author of several zkSNARK libraries, and is a co-inventor of the Zerocash protocol. He has co-founded Zcash and StarkWare Industries. He is a recipient of a Sloan Research Fellowship (2021), an Okawa Foundation Research Grant (2020), and Google Faculty Research Awards (2018 and 2017). He was included in MIT Technology Review's "35 Innovators Under 35" list in 2018.
