Silicon Valley | EPFL Graph Search

Silicon Valley is a region in Northern California that serves as a global center for high technology and innovation. Located in the southern part of the San Francisco Bay Area, it corresponds roughly to the geographical area of the Santa Clara Valley. San Jose is Silicon Valley's largest city, the third-largest in California, and the 12th-most populous in the United States. Other major Silicon Valley cities include Sunnyvale, Santa Clara, Redwood City, Mountain View, Palo Alto, Menlo Park, and Cupertino. The San Jose Metropolitan Area has the third-highest GDP per capita in the world (after Zürich, Switzerland and Oslo, Norway), according to the Brookings Institution, and, as of June 2021, has the highest percentage of homes valued at $1 million or more in the United States. Silicon Valley is home to many of the world's largest high-tech corporations, including the headquarters of more than 30 businesses in the Fortune 1000, and thousands of startup companies. Silicon Valley also acco

Metropolitan Innovation Systems: Inquiry into the co-evolving relations between Industry, University and Government

Jiayun Shen

Innovation is crucial and decisive for the long-term development of a metropolitan region in the global economy. While firms certainly play a significant role in the development of specific innovation, the environment that nur-tures innovative firms and disseminates innovations in the economy involves a complex web of interactions among a range of actors, including firms, universities, and local governments. The performance of these actors, but also their interactions, have significant impacts on the overall innovation performance of the region. The great complexity of these interactions makes it challenging for many regions to strengthen the innovation per-formance of their areas. To address this challenge, the main innovation actors â ranging from firms and universi-ties to governments â have made great efforts to learn from the famous example of Silicon Valley. However, despite some self-promotion, almost all such efforts of these regions have failed. The root of this failure lies in the lack of holistic and historical view in the learning process and the lack of proper coordination among actors in the implementation process. The existing learning about the Silicon Valley model mostly focuses on the period since the 1970s when Silicon Valleyâs success has been widely acknowledged; and it provides static analysis by listing the key features of an already successful metropolitan innovation system. While such an approach cer-tainly helps with understanding, it could be misleading, since the actors often implement the lessons learned from the advanced stage that do not fit the current stage of the region. Hence, this thesis studies the 170 years of Silicon Valleyâs development to shed light on how the actors in the three institutional spheres interact and coordi-nate in the development process. Provided that the changed global environment and the different local cultures invite the additional issue of whether the learnings are applicable to the new contexts, three case studies have been conducted in this thesis â about Beijing, Shenzhen, and Hangzhou in China â over a time span of 70 years (from 1950 to 2020). These cases are then analyzed with the framework and theory grounded from the case of Silicon Valley. Synthesizing the analysis of the four selected cases, the development path of the Metropolitan Innovation System (MIS) in Beijing most closely resembles the Silicon Valley model, since both moved from a âlaissez-faireâ model to a balanced âTriple Helixâ model (where industry, university, and government have intensive interactions and play interwoven roles). The MIS in Shenzhen reveals a path that starts from the âstatistâ model, while the one in Hangzhou started with a semi-balanced Triple Helix model. The three paths converge in the sense of heading towards the balanced Triple Helix model and all three improve the interaction and coordination between the ac-tors in the three spheres in a process that ultimately creates an open and conducive environment. This includes the ability to attract high-quality talent and cognitive capital to the region. By providing thick-descriptions of the four cases and the tentative theory about the development of MIS, this the-sis contributes to the literature of innovation system, the Triple Helix model, and the New Institutional Economics, and contributes to practice by providing 20 recommendations for the actors in the three spheres.

EPFL2020

Deep-submicron embedded processor architectures for high-performance, low-cost and low-power

Sylvain Aguirre

Because the market has an insatiable appetite for new functionality, performance is becoming an increasingly important factor. The telecommunication and network domains are especially touched by this phenomenon but they are not the only ones. For instance, the automotive applications are also affected by the passion around the electronic devices that are programmable. This thesis work will focus on embedded applications based on programmable processing unit. Indeed, nowadays, for time to market reasons, re-use and flexibility are important parameters. Consequently, embedded processors seem to be the solution because the behavior of the circuit can be modified by software what does not cost a lot compared to Application Specific Integrated Circuits (ASICs) or Digital Signal Processors (DSPs) where hardware modifications are necessary. This choice is judicious compared to multi-pipeline processors like superscalar or Very Long Instruction Word (VLIW) architectures or even in comparison to a Field Programmable Gate Array (FPGA) which require more silicon area, consume more energy and are not as robust as simple scalar processors. Nevertheless, commercial scalar processors, dedicated to embedded systems, have poor frequencies which has a negative effect on their performance. This phenomenon is even more visible with deep-submicron technologies where the primary memories and wire delays do not scale as fast as the logic. Furthermore, the memory speed decreases when their capacity of storage increases and depends on both their organization (associativity, word size, etc.) and the IPs of the foundry. Likewise, synthesizable IP memories have a greater access time than their hard macrocell counterparts. This thesis work proposes a new synthesizable architecture for scalar embedded processors dedicated to alleviate the drawbacks previously mentioned and called Memory Wall : so, its goal is to push back the limits of frequency without introducing wasted cycles used to solve data and control dependencies, independently of the foundry. The architecture that came out, called Deep Submicron RISC (DSR), is made up of a single pipeline with eight stages that executes the instructions in order. In addition to tackle the memory access time and to alleviate the delays of wires, it is appropriate to minimize the power consumption. The proposed architecture is compared to two MIPS architectures, the MIPS R3000 and the MIPS32 24k in order to be able to analyze the performance of the architectures themselves, independently of both Instruction Set (ISA) MIPS 1 and compiler. The R3000 is a processor born in the 90's and the 24k came out in 2004. Obviously, the study reveals that the five-stage processor remains efficient – especially in comparison to the MIPS24k – when the critical path passes by the core and not by the primary memories. Even if the MIPS24k tackles in part the Memory Wall, DSR is much more efficient and reach a gain of efficiency – defined as performance/surface – of 72% thanks to its High-density version (DSR-HD) compared to a five-stage processor. DSR is even more efficient than the two MIPS processors when the transistor channel length decreases, the wire delays are important or the memories are large and their organization complex.

EPFL2007

Scale-Out Processors

Pejman Lotfi Kamran

Global-scale online services, such as Google’s Web search and Facebook’s social networking, run in large-scale datacenters. Due to their massive scale, these services are designed to scale out (or distribute) their respective loads and datasets across thousands of servers in datacenters. The growing demand for online services forced service providers to build networks of datacenters, which require an enormous capital outlay for infrastructure, hardware, and power consumption. Consequently, efficiency has become a major concern in the design and operation of such datacenters, with processor efficiency being of, utmost importance, due to the significant contribution of processors to the overall datacenter performance and cost. Scale-out workloads, which are behind today’s online services, serve independent requests, and have large instruction footprints and little data locality. As such, they benefit from processor designs that feature many cores and a modestly sized Last-Level Cache (LLC), a fast access path to the LLC, and high-bandwidth interfaces to memory. Existing server-class processors with large LLCs and a handful of aggressive out-of-order cores are inefficient in executing scale-out workloads. Moreover, the scaling trajectory for these processors leads to even lower efficiency in future technology nodes. This thesis presents a family of throughput-optimal processors, called Scale-Out Processors, for the efficient execution of scale-out workloads. A unique feature of Scale-Out Processors is that they consist of multiple stand-alone modules, called pods, wherein each module is a server running an operating system and a full software stack. To design a throughput-optimal processor, we developed a methodology based on performance density, defined as throughput per unit area, to quantify how effectively an architecture uses the silicon real estate. The proposed methodology derives a performance-density optimal processor building block (i.e., pod), which tightly couples a number of cores to a small LLC via a fast interconnect. Scale-Out Processors simply consist of multiple pods with no inter-pod connectivity or coherence. Moreover, they deliver the highest throughput in today’s technology and afford near-ideal scalability as process technology advances. We demonstrate that Scale-Out Processors improve datacenters’ efficiency by 4.4x-7.1x over datacenters designed using existing server-class processors.

EPFL2013