Concept

Xeon

Related publications (58)

A High-performance FPGA Architecture Using One-Level RRAM-based Multiplexers

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang

Resistive Random Access Memory (RRAM)-based routing multiplexers, built using a one-level structure, are significantly more delay efficient than state-of-art SRAM-based implementations thanks to their lower achievable on-state resistance. In addition, the ...

2017

DRAF: A Low-Power DRAM-based Reconfigurable Acceleration Fabric

Christos Kozyrakis

FPGAs are a popular target for application-specific accelerators because they lead to a good balance between flexibility and energy efficiency. However, FPGA lookup tables introduce significant area and power overheads, making it difficult to use FPGA devi ...

Ieee2016

Leveraging a Cluster-Booster Architecture for Brain-Scale Simulations

Felix Schürmann, James Gonzalo King, Michael Lee Hines, Pramod Shivaji Kumbhar, Aleksandr Ovcharenko

The European Dynamical Exascale Entry Platform (DEEP) is an example of a new type of heterogeneous supercomputing architecture that include both a standard multicore-based "Cluster" used to run less scalable parts of an application, and an Intel MIC-based ...

Springer Int Publishing Ag2016

A portable platform for accelerated PIC codes and its application to GPUs using OpenACC

Laurent Villard, Stephan Brunner, Emmanuel Lanti, Trach-Minh Tran, Claudio Gheller

We present a portable platform, called PIC_ENGINE, for accelerating Particle-In-Cell (PIC) codes on heterogeneous many-core architectures such as Graphic Processing Units (GPUs). The aim of this development is efficient simulations on future exascale syste ...

Elsevier Science Bv2016

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

High-Voltage Tolerant Bi-State Self-Biasing Output Driver using Cascade Complementary Latches in Twin-well CMOS Technology

Scott Anthony Lindner

The design of a bi-state output buffer that can handle 5 times the supply voltage is presented. The use of self-biasing stacked devices driven by a cascade of complementary latches allows all devices to operate within the limits set by the technology, thus ...

Ieee2016

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing

Andreas Peter Burg, Adam Shmuel Teman, Luca Benini, Jeremy Hugues-Felix Constantin

Low power (mW) and high performance (GOPS) are strong requirements for compute-intensive signal processing in E-health, Internet-of-Things, and wearable applications. This work presents a building block for programmable Ultra-Low Power accelerators, namely ...

Ieee2016

A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache

Giovanni De Micheli, Luca Benini

The use of multi-core clusters is a promising option for data-intensive embedded applications such as multi-modal sensor fusion, image understanding, mobile augmented reality. In this paper, we propose a power-efficient 3-D on-chip interconnect for multi-c ...

IEEE2016

High Performance Transaction Processing on Non-Uniform Hardware Topologies

Danica Porobic

Transaction processing is a mission critical enterprise application that runs on high-end servers. Traditionally, transaction processing systems have been designed for uniform core-to-core communication latencies. In the past decade, with the emergence of ...

EPFL2016

On the Performance of Delegation over Cache-Coherent Shared Memory

André Schiper, Thomas Ropars, Darko Petrovic

Delegation is a thread synchronization technique where access to shared data is performed through a dedicated server thread. When a client thread requires shared data access, it makes a request to a server and waits for a response. This paper studies deleg ...

2015

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.