Concept

Glossary of computer hardware terms

Related publications (27)

Design Space Exploration for Partitioning Dataflow Program on CPU-GPU Heterogeneous System

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Dataflow programming is a methodology that enables the development of high-level, parametric programs that are independent of the underlying platform. This approach is particularly useful for heterogeneous platforms, as it eliminates the need to rewrite ap ...

SPRINGER2023

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Aurélien François Gilbert Bloch

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

EPFL2023

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Current Dynamic Texture Synthesis (DyTS) models can synthesize realistic videos. However, they require a slow iterative optimization process to synthesize a single fixed-size short video, and they do not offer any post-training control over the synthesis p ...

2023

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Los Alamitos2023

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Writing and optimizing application software for heterogeneous platforms including GPU units is a very difficult task that requires designer efforts and resources to consider several key elements to obtain good performance. Dataflow programming has shown to ...

2022

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

The performance of programs executed on heterogeneous parallel platforms largely depends on the design choices regarding how to partition the processing on the various different processing units. In other words, it depends on the assumptions and parameters ...

MDPI2022

Atomic object reads for in-memory rack-scale computing

Babak Falsafi, Boris Robert Grot, Alexandros Daglis

A distributed memory system including a plurality of chips, a plurality of nodes that are distributed across the plurality of chips such that each node is comprised within a chip, each node includes a dedicated local memory and a processor core, and each l ...

2018

Dynamic NoC buffer allocation for MPSoC timing side channel attack protection

Mathias Soeken

Multi-Processors Systems-on-Chip (MPSoCs), as a key technology enabler of the new computation paradigm Internet-of-Things (IoT), are exposed to attacks. Malicious applications can be downloaded at runtime to the MPSoC, infect IPs and open doors to perform ...

IEEE2016

High Performance Transaction Processing on Non-Uniform Hardware Topologies

Danica Porobic

Transaction processing is a mission critical enterprise application that runs on high-end servers. Traditionally, transaction processing systems have been designed for uniform core-to-core communication latencies. In the past decade, with the emergence of ...

EPFL2016

Eddy current induction is used in a wide range of electronic devices, for example in detection sensors. Due to the advances in computer hardware and software, the need for 3D computation and system comprehension is a requirement to develop and optimize suc ...

2014

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