Publications related to Power management

A 16-Channel 60µW Neural Synchrony Processor for Multi-Mode Phase-Locked Neurostimulation

Mahsa Shoaran, Uisub Shin, Cong Ding, Laxmeesha Somappa

Measuring neural oscillatory synchrony facilitates our understanding of complex brain networks and the underlying pathological states. Altering the cross-regional synchrony-as a measure of brain network connectivity-via phase-locked deep brain stimulation ...

IEEE2022

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Robert Giterman

Side-channel attacks constitute a concrete threat to IoT systems-on-a-chip (SoCs). Embedded memories implemented with 6T SRAM macrocells often dominate the area and power consumption of these SoCs. Regardless of the computational platform, the side-channel ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Gem5-X : A Many-Core Heterogeneous Simulation Platform for Architectural Exploration and Optimization

David Atienza Alonso, Marina Zapater Sancho, William Andrew Simon, Yasir Mahmood Qureshi

The increasing adoption of smart systems in our daily life has led to the development of new applications with varying performance and energy constraints, and suitable computing architectures need to be developed for these new applications. In this paper, ...

2021

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

Mirjana Stojilovic, Hossein Asadi, Zeinab Seifoori

Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the ...

2021

A Low Power 35 GHz HEMT Oscillator for Electron Spin Resonance Spectroscopy

Giovanni Boero, Nergiz Sahin Solmaz, Alessandro Valentino Matheoud

This paper presents a low power microwave oscillator designed as sensor for electron spin resonance (ESR) spectroscopy. Low power consumption is necessary for low temperature operation. Additionally, lower power consumption allows for a lower microwave mag ...

IEEE2021

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Mohamed Mostafa Sabry Aly, Halima Najibi

Deeply-scaled three-dimensional (3D) Multi-Processor Systems-on-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However, as process nodes shrink, temperature-dependent leakage dramatically increases, ...

2020

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, William Andrew Simon

Hybrid caches consisting of both SRAM and emerging Non-Volatile Random Access Memory (eNVRAM) bitcells increase cache capacity and reduce power consumption by taking advantage of eNVRAM's small area footprint and low leakage energy. However, they also inhe ...

2020

MEMS-Enabled Silicon Photonic Integrated Devices and Circuits

Niels Quack, Hamed Sattari, Alain Yuji Takabayashi, Yu Zhang

Photonic integrated circuits have seen a dramatic increase in complexity over the past decades. This development has been spurred by recent applications in datacenter communications and enabled by the availability of standardized mature technology platform ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

GPU-accelerated data management under the test of time

Anastasia Ailamaki, Syed Mohammad Aunn Raza, Periklis Chrysogelos, Angelos Christos Anadiotis, Panagiotis Sioulas

GPUs are becoming increasingly popular in large scale data center installations due to their strong, embarrassingly parallel, processing capabilities. Data management systems are riding the wave by using GPUs to accelerate query execution, mainly for analy ...

2020

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Power management

A 16-Channel 60µW Neural Synchrony Processor for Multi-Mode Phase-Locked Neurostimulation

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Gem5-X : A Many-Core Heterogeneous Simulation Platform for Architectural Exploration and Optimization

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

A Low Power 35 GHz HEMT Oscillator for Electron Spin Resonance Spectroscopy

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

At the end of scaling: 2D materials for computing and sensing applications

MEMS-Enabled Silicon Photonic Integrated Devices and Circuits

GPU-accelerated data management under the test of time

Graph Chatbot

Chat with Graph Search

A 16-Channel 60µW Neural Synchrony Processor for Multi-Mode Phase-Locked Neurostimulation

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Gem5-X : A Many-Core Heterogeneous Simulation Platform for Architectural Exploration and Optimization

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

A Low Power 35 GHz HEMT Oscillator for Electron Spin Resonance Spectroscopy

A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance

At the end of scaling: 2D materials for computing and sensing applications

MEMS-Enabled Silicon Photonic Integrated Devices and Circuits

GPU-accelerated data management under the test of time