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Concept
FR-V (microprocessor)
Summary
The Fujitsu FR-V (Fujitsu RISC-VLIW) is one of the very few processors ever able to process both a very long instruction word (VLIW) and vector processor instructions at the same time, increasing throughput with high parallel computing while increasing performance per watt and hardware efficiency. The family was presented in 1999. Its design was influenced by the VPP500/5000 models of the Fujitsu VP/2000 vector processor supercomputer line.
Featuring a 1–8 way very long instruction word (VLIW, Multiple Instruction Multiple Data (MIMD), up to 256 bit) instruction set it additionally uses a 4-way single instruction, multiple data (SIMD) vector processor core. A 32-bit RISC instruction set in the superscalar core is combined with most variants integrating a dual 16-bit media processor also in VLIW and vector architecture. Each processor core is superpipelined as well as 4-unit superscalar.
A typical integrated circuit integrates a system on a chip and further multiplies speed by integrating multiple cores. Due to the very low power requirements it is a solution even for battery-powered applications.
The family started with the FR-500, includes FR-300, FR-400, FR-450, FR-550 and FR1000 architecture 32-bit processors, can run Linux, RTLinux, VxWorks, eCos, or ITRON and is also supported by the Softune Integrated development environment and the GNU Compiler Collection or GNUPro.
It is often used for or video processing with most variants including a dual 16-bit media-processor.
The 2005 presented FR1000 uses a core with 8-way 256-bit VLIW (MIMD) filling its superpipeline as well as a 4-unit superscalar architecture (Integer (ALU)-, Floating-point- and two media-processor-units), further increasing its peak performance of each core to up to 28 instructions per clock cycle. Like other VLIW-architectures 1 way is needed to load the next 256-bit instruction: 7-ways usable. Due to the used 4-way single instruction, multiple data (SIMD) vector processor-core, it counts to up to 112 data-operations per cycle and core.
Official source
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