Publications related to Atom (system on a chip)

3D Thermal-Aware Floorplanner for Many-Core Single-Chip Systems

David Atienza Alonso, José Luis Ayala Rodrigo

Heat removal and power density distribution delivery have become two major reliability concerns in 3D stacked technology. In this paper, we propose a thermal-driven 3D floorplanner. Our contributions include: (1) a novel multi-objective formulation to cons ...

IEEE Press2011

Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

In many of today’s system-on-chip (SoC) designs, the cores are partitioned into multiple voltage and frequency islands (VFIs), and the global interconnect is implemented using a packetswitched network on chip (NoC). In such VFI-based designs, the benefits ...

Institute of Electrical and Electronics Engineers2010

Run-time Mapping of Applications on FPGA-based Reconfigurable Systems

David Atienza Alonso, Ivan Beretta

The role of Field-Programmable Gate Arrays (FPGAs) in System-on-Chip (SoC) design considerably increased in the last few years. Their established importance is due to the large amount of hardware resources they offer, as well as to their increasing perform ...

IEEE Press2010

A Method to Remove Deadlocks in Networks-on-Chips with Wormhole Flow Control

Giovanni De Micheli, Luca Benini, Srinivasan Murali, Ciprian Seiculescu

Networks-on-Chip (NoCs) are a promising interconnect paradigm to address the communication bottleneck of Systems-on-Chip (SoCs). Wormhole flow control is widely used as the transmission protocol in NoCs, as it offers high throughput and low latency. To mat ...

2010

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Giovanni De Micheli, David Atienza Alonso

Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systems-on-Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of runn ...

Springer2010

A Low-Noise CMOS Receiver Frontend for NMR-based Surgical Guidance

Giovanni Boero, Jens Anders

In this paper a novel architecture for an integrated NMR receiver front-end for surgical guidance applications is described. While the chip consumes only 9 mA supply current from a 3.3 V power supply it has a measured input referred noise density of 0.7 nV ...

Springer, 233 Spring Street, New York, Ny 10013, United States2009

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

David Atienza Alonso, Luca Benini, Srinivasan Murali

Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhanced support for dynamic and partial reconfigurability. Design automation suppor ...

IEEE Press2009

A Low-Noise CMOS Receiver Frontend for MRI

Giovanni Boero, Jens Anders

In this paper a novel architecture for an integrated receiver front-end for micro magnetic resonance imaging (micro-MRI) applications is described. While the chip consumes only 9mA supply current (4mA in the LNA and 5mA in the output buffer) from a 33V pow ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008

Features extraction for low-power face verification

Patrick Stadelmann

Mobile communication devices now available on the market, such as so-called smartphones, are far more advanced than the first cellular phones that became very popular one decade ago. In addition to their historical purpose, namely enabling wireless vocal c ...

University of Neuchâtel2008

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Atom (system on a chip)

3D Thermal-Aware Floorplanner for Many-Core Single-Chip Systems

Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands

Run-time Mapping of Applications on FPGA-based Reconfigurable Systems

A Method to Remove Deadlocks in Networks-on-Chips with Wormhole Flow Control

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

A Low-Noise CMOS Receiver Frontend for NMR-based Surgical Guidance

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

Structural Studies of the Ionic Liquid 1-Ethyl-3-methylimidazolium Tetrafluoroborate in Dichloromethane Using a Combined DFT-NMR Spectroscopic Approach

A Low-Noise CMOS Receiver Frontend for MRI

Features extraction for low-power face verification

Graph Chatbot

Chat with Graph Search

Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

3D Thermal-Aware Floorplanner for Many-Core Single-Chip Systems

A Low-Noise CMOS Receiver Frontend for MRI

A Low-Noise CMOS Receiver Frontend for NMR-based Surgical Guidance

Run-time Mapping of Applications on FPGA-based Reconfigurable Systems

Structural Studies of the Ionic Liquid 1-Ethyl-3-methylimidazolium Tetrafluoroborate in Dichloromethane Using a Combined DFT-NMR Spectroscopic Approach

A Method to Remove Deadlocks in Networks-on-Chips with Wormhole Flow Control

Features extraction for low-power face verification

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems