Publications related to Systolic array

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi, Joshua Alexander Harrison Klein

Transformer models have achieved impressive results in various AI scenarios, ranging from vision to natural language processing. However, their computational complexity and their vast number of parameters hinder their implementations on resource-constraine ...

2023

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Aurélien François Gilbert Bloch

Today's continued increase in demand for processing power, despite the slowdown of Moore's law, has led to an increase in processor count, which has resulted in energy consumption and distribution problems. To address this, there is a growing trend toward ...

EPFL2023

Tradeoffs in Low-Power Accelerators Design for Large-Scale Interferometers

David Atienza Alonso, Miguel Peon Quiros, Denisa-Andreea Constantinescu, Benoît Walter Denkinger

Large-scale scientific infrastructures like SKAO—the world’s largest radio observatory for the coming decades—are generating massive-scale data streams of multi-Tb/s to be processed using complex interferometry algorithms. Concretely, SKAO is expected to g ...

2023

Thermal and Power-Aware Run-Time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Alexandre Sébastien Julien Levisse, Halima Najibi

Flow Cell Arrays (FCA) technology employs microchannels filled with an electrolytic fluid to concurrently provide cooling and power generation to integrated circuits (ICs). This solution is particularly appealing for Three-Dimensional Multi-Processor Syste ...

2022

Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Developing and fine-tuning software programs for heterogeneous hardware such as CPU/GPU processing platforms comprise a highly complex endeavor that demands considerable time and effort of software engineers and requires evaluating various fundamental comp ...

MDPI2022

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Marco Mattavelli, Simone Casale Brunet, Aurélien François Gilbert Bloch

Writing and optimizing application software for heterogeneous platforms including GPU units is a very difficult task that requires designer efforts and resources to consider several key elements to obtain good performance. Dataflow programming has shown to ...

2022

BLADE: A BitLine Accelerator for Devices on the Edge

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, William Andrew Simon, Yasir Mahmood Qureshi

The increasing ubiquity of edge devices in the consumer market, along with their ever more computationally expensive workloads, necessitate corresponding increases in computing power to support such workloads. In-memory computing is attractive in edge devi ...

2019

Exploiting Flow Graph of System of ODEs to Accelerate the Simulation of Biologically-Detailed Neural Networks

Felix Schürmann, Michael Lee Hines, Bruno Ricardo Da Cunha Magalhães

Exposing parallelism in scientific applications has become a core requirement for efficiently running on modern distributed multicore SIMD compute architectures. The granularity of parallelism that can be attained is a key determinant for the achievable ac ...

IEEE2019

Hardware-conscious Hash-Joins on GPUs

Anastasia Ailamaki, Periklis Chrysogelos, Panagiotis Sioulas, Manolis Karpathiotakis, Raja Appuswamy

Traditionally, analytical database engines have used task parallelism provided by modern multisocket multicore CPUs for scaling query execution. Over the past few years, GPUs have started gaining traction as accelerators for processing analytical queries d ...

IEEE2019

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Systolic array

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

Hardware-Software Co-design for Improved Resource Utilization in DNN Accelerators

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Tradeoffs in Low-Power Accelerators Design for Large-Scale Interferometers

Thermal and Power-Aware Run-Time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays

Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

BLADE: A BitLine Accelerator for Devices on the Edge

Exploiting Flow Graph of System of ODEs to Accelerate the Simulation of Biologically-Detailed Neural Networks

Hardware-conscious Hash-Joins on GPUs

Graph Chatbot

Chat with Graph Search

Thermal and Power-Aware Run-Time Performance Management of 3D MPSoCs with Integrated Flow Cell Arrays

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

Compilation and Design Space Exploration of Dataflow Programs for Heterogeneous CPU-GPU Platforms

Hardware-Software Co-design for Improved Resource Utilization in DNN Accelerators

Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

BLADE: A BitLine Accelerator for Devices on the Edge

Hardware-conscious Hash-Joins on GPUs

Tradeoffs in Low-Power Accelerators Design for Large-Scale Interferometers

SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Exploiting Flow Graph of System of ODEs to Accelerate the Simulation of Biologically-Detailed Neural Networks