Concept

Sense amplifier

Related publications (16)

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped p ...

Elsevier2014

Dynamic stability and noise margins of SRAM arrays in nanoscaled technologies

Adam Shmuel Teman

SRAM stability is one of the primary bottlenecks of current VLSI system design, and the unequivocal supply voltage scaling limiter. Static noise margin metrics have long been the de-facto standard for measuring this stability and estimating the yield of SR ...

IEEE2014

Semiconductor memory cell, array, architecture and device, and method of operating same

Serguei Okhonin

There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of ...

2007

Reducing leakage in a high-performance deep-submicron instruction cache

Babak Falsafi

Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold ...

2001

An integrated circuit/architecture approach to reducing leakage in deep-submicron high-performance I-caches

Babak Falsafi

Deep-submicron CMOS designs maintain high transistor switching speeds by scaling down the supply voltage and proportionately, reducing the transistor threshold voltage. Lowering the threshold voltage increases leakage energy dissipation due to subthreshold ...

2001

Gated-Vdd: a circuit technique to reduce leakage in deep- submicron cache memories

Babak Falsafi

Deep-submicron CMOS designs have resulted in large leakage energy dissipation in microprocessors. While SRAM cells in on-chip cache memories always contribute to this leakage, there is a large variability in active cell usage both within and across applica ...

2000

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