Publications related to SPARC | EPFL Graph Search

Control-Flow Hijacking attacks are the dominant attack vector against C/C++ programs. Control-Flow Integrity (CFI) solutions mitigate these attacks on the forward edge, i.e., indirect calls through function pointers and virtual calls. Protecting the backwa ...

IEEE COMPUTER SOC2019

Trading off Energy versus Accuracy in Modern Computing Systems

Jérémy Lucien Maurice Schlachter

The slowdown of Moore's law, which has been the driving force of the electronics industry over the last 5 decades, is causing serious problem to Integrated Circuits (ICs) improvements. Technology scaling is becoming more and more complex and fabrication co ...

EPFL2018

HEAL-WEAR: an Ultra-Low Power Heterogeneous System for Bio-Signal Analysis

David Atienza Alonso, Giovanni Ansaloni, Ruben Braojos Lopez, Soumya Subhra Basu, Loris Gérard Duch

Personalized healthcare devices enable low-cost, unobtrusive and long-term acquisition of clinically-relevant biosignals. These appliances, termed Wireless Body Sensor Nodes (WBSNs), are fostering a revolution in health monitoring for patients affected by ...

Ieee-Inst Electrical Electronics Engineers Inc2017

Approximate 32-Bit Floating-Point Unit Design with 53% Power-Area Product Reduction

Christian Enz, Vincent Frédéric Camus, Jérémy Lucien Maurice Schlachter

The floating-point unit is one of the most common building block in any computing system and is used for a huge number of applications. By combining two state-of-the-art techniques of imprecise hardware, namely Gate-Level Pruning and Inexact Speculative Ad ...

Ieee2016

A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications

Adam Shmuel Teman, Robert Giterman, Pascal Andreas Meinerzhagen

Continuous transistor scaling, coupled with the growing demand for low-voltage, low-power applications, increases the susceptibility of VLSI circuits to soft-errors, especially when exposed to extreme environmental conditions, such as those encountered by ...

Institute of Electrical and Electronics Engineers2016

The EPFL Combinational Benchmark Suite

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

In this paper, we present the EPFL combinational benchmark suite. We aim at completing existing benchmark suites by focusing only on natively combinational benchmarks. The EPFL combinational benchmark suite consists of 23 combinational circuits desi ...

2015

Manual Parallelization Versus State-of-the-Art Parallelization Techniques: The SPEC CPU2006 as a Case Study

Aleksandar Vitorovic

Being multiprocessors (both on-chip and/or off-chip), modern computer systems can automatically exploit the benefits of parallel programs, but their resources remain underutilized in executing still-Prevailing sequential applications. An obvious solution i ...

Elsevier Academic Press Inc2014

Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing

David Atienza Alonso, Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Ahmed Yasir Dogan

A multi-core architecture with ultra-low power consumption is needed for a wide variety of applications, especially in the bio-medical domain. In this patent, an ultra-low power multi-core architecture is presented: it is composed of one or more cores, sev ...

2014

JPaxos: State machine replication based on the Paxos protocol

André Schiper, Nuno Filipe de Sousa Santos

State machine replication is a technique for making services fault-tolerant by replicating them over a group of machines. Although the theory of state machine replication has been studied extensively, the engineering challenges of converting a theoretical ...

2011

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SPARC

SoK: Shining Light on Shadow Stacks

Trading off Energy versus Accuracy in Modern Computing Systems

HEAL-WEAR: an Ultra-Low Power Heterogeneous System for Bio-Signal Analysis

Approximate 32-Bit Floating-Point Unit Design with 53% Power-Area Product Reduction

A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications

The EPFL Combinational Benchmark Suite

A Thrifty Universal Construction

Manual Parallelization Versus State-of-the-Art Parallelization Techniques: The SPEC CPU2006 as a Case Study

Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing

JPaxos: State machine replication based on the Paxos protocol

Graph Chatbot

Chat with Graph Search

SoK: Shining Light on Shadow Stacks

Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing

A Thrifty Universal Construction

Approximate 32-Bit Floating-Point Unit Design with 53% Power-Area Product Reduction

HEAL-WEAR: an Ultra-Low Power Heterogeneous System for Bio-Signal Analysis

Trading off Energy versus Accuracy in Modern Computing Systems

Manual Parallelization Versus State-of-the-Art Parallelization Techniques: The SPEC CPU2006 as a Case Study

A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications

The EPFL Combinational Benchmark Suite

JPaxos: State machine replication based on the Paxos protocol