Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.
DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.
A simple and fast process for micro-electromechanical (MEM) resonators with deep sub-micron transduction gaps in thin SOI is presented in this paper. Thin SOI wafers are important for advanced CMOS technology and thus are evaluated as resonator substrates ...
Cutting-edge CMOS neurochips, which consist of a Microelectrode Array (MEA) manufactured on top of CMOS circuitry, allow the recording of the electrical activity of neural networks in-vitro, and their stimulation. As CMOS technology continues to scale down ...
Many hardware optimizations rely on collecting information about program behavior at runtime. This information is stored in lookup tables. To be accurate and effective, these optimizations usually require large dedicated on-chip tables. Although technology ...
In this paper a novel architecture for an integrated receiver front-end for micro magnetic resonance imaging (micro-MRI) applications is described. While the chip consumes only 9mA supply current (4mA in the LNA and 5mA in the output buffer) from a 33V pow ...
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2008
[...] During this project, the fusion feasibility of chips produced for other applications have been tested and some critical fusion parameters have been defined. Then, with the help of FEM simulations, a new chip design has been proposed to overcome the p ...
In this paper, we present an experimental current-mode Kohonen neural network (KNN) implemented in a CMOS 0.18 μm process. The network contains four output neurons. Each neuron has three analog weights related to three inputs. The presented KNN has been re ...
On-chip implementation of multiprocessor systems needs to planarise the interconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor Systems on Chips (MPSoC) node processors are homogeneous, and MPSoC n ...
This paper describes the implementation of a 12-bit 230 MS/s pipelined ADC using a conventional 1.8V, 0.18μm digital CMOS process. Two-stage folded cascode OTA topology is used for improved settling performance. Extreme low-skew (less than 3ps peak-to-peak ...
For the past couple of decades the desire to add more complexity to a computer chip, while simultaneously reducing the cost per bit, has been accommodated by down-scaling. This approach has been extremely successful in the past, but like all good things it ...
Multiple-input multiple-output (MIMO) detection algorithms providing soft information for a subsequent channel decoder pose significant implementation challenges due to their high computational complexity. In this paper, we show how sphere decoding can be ...
