Concept

Heterogeneous System Architecture

Related publications (64)

Methodology for the Hardware/Software Co-Design of Dataflow Programs

Marco Mattavelli, Ghislain Roquier, Richard Thavot

New generations of multi-core processors and reconfigurable hardware platforms are expected to provide a dramatic increase of processing capabilities. However, one obstacle for exploiting all the promises of such new platforms is the legacy of current appl ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Methodology For The Hardware/Software Co-Design Of Dataflow Programs

Marco Mattavelli, Ghislain Roquier, Richard Thavot

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

EGRA: A Coarse Grained Reconfigurable Architectural Template

Giovanni Ansaloni

Reconfigurable arrays combine the benefit of spatial execution, typical of hardware solutions, with that of programmability, present in microprocessors. When mapping software applications (or parts of them) onto hardware, however, fine-grain arrays, such a ...

2011

Fast Software AES Encryption

Joppe Willem Bos, Dag Arne Osvik, Deian Stefan

This paper presents new software speed records for AES-128 encryption for architectures at both ends of the performance spectrum. On the one side we target the low-end 8-bit AVR rnicrocontrollers and 32-bit ARM microprocessors, while on the other side of t ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

Formalizing and verifying transactional memories

Vasu Singh

Transactional memory (TM) has shown potential to simplify the task of writing concurrent programs. TM shifts the burden of managing concurrency from the programmer to the TM algorithm. The correctness of TM algorithms is generally proved manually. The goal ...

EPFL2010

ECC2K-130 on Cell CPUs

Joppe Willem Bos, Thorsten Kleinjung

This paper describes an implementation of Pollard's rho algorithm to compute the elliptic curve discrete logarithm for the Synergistic Processor Elements of the Cell Broadband Engine Architecture. Our implementation targets the elliptic curve discrete loga ...

Springer-Verlag New York, Ms Ingrid Cunningham, 175 Fifth Ave, New York, Ny 10010 Usa2010

High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms

Marco Mattavelli, Christophe Lucarz, Ghislain Roquier

Nowadays, the design flow of complex signal processing embedded systems starts with a specification of the application by means of a large and sequential program (usually in C/C++). As we are entering in the multicore era, sequential programs are no longer ...

2010

Rapid Design Space visualisation through hardware/software partitioning

Daniel Kuhn

This paper introduces the 3SP Design Space Exploration System. 3SP automatically quantifies acceleration opportunities for programs across a wide range of heterogeneous architectures to allow designers to identify promising implementation platforms before ...

IEEE2009

Mapping and Physical Planning of Networks-on-Chip Architectures with Quality-of-Service Guarantees

Giovanni De Micheli, Luca Benini, Srinivasan Murali

Networks on Chips (NoCs) have evolved as the communication design paradigm of future Systems on Chips (SoCs). In this work we target the NoC design of complex SoCs with heterogeneous processor/memory cores, providing Quality-of-Service (QoS) for the applic ...

2005

Communication Infrastructure Design for Wide-Area Mobile Computation: Specification in Nomadic Pict

We review an example of wide-area mobile agent applications: video-on-demand, long-lived scientific computation, and collaborative work, and the design of a distributed infrastructure required in each of these applications for location-independent communic ...

2005

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