Concept

Kepler (microarchitecture)

Related publications (26)

Gyrokinetic simulations of turbulence in magnetic fusion plasmas using a delta-f PIC scheme with evolving background

Using the GKEngine code which simulates an electrostatic plasma with adiabatic electron response under a sheared-slab geometry, an attempt at developing a hybrid approach between the delta-f and full-f schemes to describe plasma profiles exhibiting high fl ...

EPFL2024

Efficient Analytical Query Processing on CPU-GPU Hardware Platforms

Periklis Chrysogelos

Timely insights lead to business growth and scientific breakthroughs but require analytical engines that cope with the ever-increasing data processing needs. Analytical engines relied on rapid CPU improvements, yet the end of Dennard scaling stopped the fr ...

EPFL2022

High Performance Computing for gravitational lens modeling: Single vs double precision on GPUs and CPUs

Jean-Paul Richard Kneib, Markus Rexroth

Strong gravitational lensing is a powerful probe of cosmology and the dark matter distribution. Efficient lensing software is already a necessity to fully use its potential and the performance demands will only increase with the upcoming generation of tele ...

ELSEVIER2020

Mo(2)Cap(2): Real-time Mobile 3D Motion Capture with a Cap-mounted Fisheye Camera

Pascal Fua, Helge Jochen Rhodin

We propose the first real-time system for the egocentric estimation of 3D human body pose in a wide range of unconstrained everyday activities. This setting has a unique set of challenges, such as mobility of the hardware setup, and robustness to long capt ...

2019

A 30-frames/s, 252 x 144 SPAD Flash LiDAR With 1728 Dual-Clock 48.8-ps TDCs, and Pixel-Wise Integrated Histogramming

Edoardo Charbon, Ivan Michel Antolovic, Chunmin Zhang, Scott Anthony Lindner, Juan Mata Pavia, Martin Wolf

A 252 x 144 single-photon avalanche diode (SPAD) pixel sensor, called Ocelot, is reported for light detection and ranging (LiDAR). The sensor, fabricated in the 180-nm CMOS technology, features 1728 12-bit time-to-digital converters (TDCs) with 48.8-ps res ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Exploiting Flow Graph of System of ODEs to Accelerate the Simulation of Biologically-Detailed Neural Networks

Felix Schürmann, Michael Lee Hines, Bruno Ricardo Da Cunha Magalhães

Exposing parallelism in scientific applications has become a core requirement for efficiently running on modern distributed multicore SIMD compute architectures. The granularity of parallelism that can be attained is a key determinant for the achievable ac ...

IEEE2019

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Andrea Bonetti

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...

EPFL2019

HetExchange: Encapsulating heterogeneous CPU-GPU parallelism in JIT compiled engines

Anastasia Ailamaki, Periklis Chrysogelos, Manolis Karpathiotakis, Raja Appuswamy

Modern server hardware is increasingly heterogeneous as hardware accelerators, such as GPUs, are used together with multicore CPUs to meet the computational demands of modern data analytics workloads. Unfortunately, query parallelization techniques used by ...

2019

GPU-Accelerated Finite Volume Particle Simulation of Free Jet Deviation by Multi-jet Rotating Pelton Runner

Siamak Alimirzazadeh

Numerical simulation of Pelton turbine hydrodynamics is helpful to identify the energy loss mechanisms in the runner and minimize their effect. However, it is a challenging task that involves handling the unsteady free surface flow and moving boundaries re ...

EPFL2019

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

Yunho Oh

Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To increase the per-warp cache size prior techniques proposed warp throttling which limits the number of active warps. Warp thr ...

ASSOC COMPUTING MACHINERY2019

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