Substrate coupling

Summary

In an integrated circuit, a signal can couple from one node to another via the substrate. This phenomenon is referred to as substrate coupling or substrate noise coupling. The push for reduced cost, more compact circuit boards, and added customer features has provided incentives for the inclusion of analog functions on primarily digital MOS integrated circuits (ICs) forming mixed-signal ICs. In these systems, the speed of digital circuits is constantly increasing, chips are becoming more densely packed, interconnect layers are added, and analog resolution is increased. In addition, recent increase in wireless applications and its growing market are introducing a new set of aggressive design goals for realizing mixed-signal systems. Here, the designer integrates radio frequency (RF) analog and base band digital circuitry on a single chip. The goal is to make single-chip radio frequency integrated circuits (RFICs) on silicon, where all the blocks are fabricated on the same chip. One

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Computer aided analysis of parasitic substrate coupling in mixed digital-analog CMOS integrated circuits

EPFL1996

Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs

Pietro Buccella, Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci

A 3-D simulation of substrate currents is crucial to analyze parasitic coupling effects due to minority carrier injection in smart power ICs. In this paper, a substrate parasitic extraction methodology is introduced by dividing the IC layout into elementary elements to solve the continuity equation for minority carriers in the volume based on the finite-difference method. A substrate parasitic network is derived from the mesh generated through the existing mixed-signal design flow. The induced substrate model is included in circuit simulators such as SPICE to predict the effects of substrate couplings during the design phase. Furthermore, this analysis enables optimization of layout with minimal parasitic effects. By linking the substrate model to the active components, the couplings between the integrated circuit with the substrate parasitic currents can be analyzed during circuit simulations. Simulations and measurements on an high voltage driver reveal consistent results and therefore confirm the validity of the method. Therefore, the approach developed herein is effective to predict parasitic couplings due the injection of minority carriers.

Ieee-Inst Electrical Electronics Engineers Inc2016

Safety requirements for modern automotive electronics call for more and more robust power integrated circuits. The mixed-signal IC design flow alone is often no longer capable of tracking possible design failures in complex Smart Power integrated circuits that are caused by substrate current couplings, and consequently, the use of device simulators has become commonplace. Traditionally, for full chip simulations, device simulations are carried out on a simplified model of the substrate. It is, however, not possible to obtain precise results with this approach because IC functionalities are excluded from substrate device co-simulations that are caused by the lack of back annotation of the circuit with the substrate. In this thesis, a novel substrate extraction methodology which is fully compatible with the conventional CAD design tools is investigated. The IC layout and the technological parameters are used to build an equivalent network of the substrate that is made of lumped elements that model parasitic BJTs. The proposed substrate extraction methodology is suitable for any Smart Power technology, including HV-CMOS and BCD processes. The substrate extraction procedure is based on two major steps. First, the IC layout surface is discretized with a novel non-uniform mesh procedure in order to extract model geometrical parameters and at the same time minimize the number of extracted nodes. Then, according to the applied mesh, an equivalent three-dimensional model of the substrate is extracted and back-annotated to the circuit schematic. The overall procedure is designed to be compatible with today's design CAD tools. The methodology was validated with an integrated circuit that was realized with a HV-CMOS 0.35um technology. Experimental measurements of substrate currents due to single or parallel activation of substrate BJTs were reproduced by SPICE simulation, thus confirming the activation of a latch-up in a specific case. To address the general problem of robust IC design, a fast method to monitor substrate currents is also presented. Substrate extraction is performed during the preliminary design phase in order to identify any critical substrate current path and to minimize related risks with a precise placement of protections in an optimal layout floorplan. This approach has also proved to be an efficient tool for designing and characterizing the effectiveness of passive and active protections. The developed methodology precisely and efficiently minimizes substrate couplings in Smart Power ICs. As a result, designs with a high degree of immunity to substrate currents can be achieved rapidly within the design flow, thus avoiding expensive re-designs.

EPFL2016