Related publications (451)

A 4.1 pJ/b 25.6 Gb/s 4-PAM Reduced-State Sliding-Block Viterbi Detector in 14 nm CMOS

Andreas Peter Burg, Lukas Kull, Thomas Toifl, Giovanni Cherubini

The implementation of a digital four-level pulse-amplitude-modulation reduced-state sliding-block Viterbi detector (VD) with two substates and two embedded per-survivor decision-feedback taps operating at one-eighth of the modulation rate is described. Imp ...
Ieee2016

High-Speed Link With Trellis-Coded Modulation and Reed Solomon Coding

Andreas Peter Burg, Thomas Toifl, Giovanni Cherubini

A high-performance low-latency transmission system based on a concatenated code consisting of inner four-dimensional five-level pulse-amplitude-modulation (5-PAM) trellis-coded modulation and an outer Reed-Solomon (RS) code is proposed for a high-speed dat ...
Ieee2016

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